A semiconductor device includes a semiconductor-on-insulator wafer having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

This composite substrate has a single-crystal semiconductor thin film (13) provided to at least the front surface of an inorganic insulating sintered-body substrate (11) having a thermal conductivity of at least 5 W/m.Math.K and a volume resistivity of at least 110.sup.8 .Math.cm. The composite substrate also has, provided between the inorganic insulating sintered-body substrate (11) and the single-crystal semiconductor thin film (13), a silicon coating layer (12) comprising polycrystalline silicon or amorphous silicon. As a result of the present invention, metal impurity contamination from the sintered body can be inhibited, even in a composite substrate in which a single-crystal silicon thin film is provided upon an inexpensive ceramic sintered body which is opaque with respect to visible light, which exhibits an excellent thermal conductivity, and which further exhibits little loss at a high frequency range, and characteristics can be improved.

There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.

A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.

A quasi-lateral diffusion transistor is formed in a semiconductor-on-insulator (SOI) wafer by forming a gate region, a body region, a drift region, and a source region and bonding a handle wafer to the SOI wafer at a first side (e.g., top side) of the SOI wafer; and removing a semiconductor substrate of the SOI wafer, forming a hole in a buried insulator layer of the SOI wafer, and forming a drain region for the transistor at a second side (e.g., bottom side) of the SOI wafer. The body region and the drift region physically contact the buried insulator layer. The drain region is formed in a bottom portion of the drift region exposed by the hole and is laterally offset from the source region. In operation of the quasi-lateral diffusion transistor, a current flow direction through the semiconductor layer is diagonal between the source region and the drain region.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.