A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins, and the second fins; and removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the second fin covered by a remaining portion of the first mask layer being a second fin device region.

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the substrate and at least one semiconductor fin between the trenches; forming a plurality of insulators in the trenches; forming a patterned photoresist on the insulators, wherein sidewalls of the semiconductor fin are partially covered by the patterned photoresist, and at least one area of the sidewalls is exposed by the patterned photoresist; by using the patterned photoresist as a mask, partially removing the semiconductor fin from the at least one area of the sidewalls exposed by the patterned photoresist so as to form at least one recess on the sidewalls of the semiconductor fin; removing the patterned photoresist after forming the at least one recess; and forming a gate stack to partially cover the semiconductor fin and the insulators.

A FinFET system comprises a first inverter comprising a first p-type pull-up transistor (PU) and a first n-type pull-down transistor (PD connected in series with the first PD, a second inverter cross-coupled to the first inverter comprising a second PU and a second PD connected in series with the second PD, a first pass-gate transistor, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line, a second pass-gate transistor, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line, a first dummy transistor coupled to a first common node of the first PU and the first PD and a second dummy transistor coupled to a second common node of the second PU and the second PD.

A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.