An electrostatic discharge (ESD) protection system of a micro device is disclosed. The ESD protection system comprises: a pixel driver circuit, electrically connected to at least one micro LED pixel for controlling the turning-on or off of the micro LED pixel, and a first ESD protective unit, electrically connected to a first level voltage (Vdd) and the second level voltage (Vcom). In some embodiments, the micro LED pixel is electrically connected to a second level voltage (Vcom). The ESD protection system can protect the micro LED pixel from being damaged by the electrostatic discharge. Various embodiments include an ESD protection system of a display panel with a micro-LED pixel array.

The present disclosure provides a nonvolatile storage device and a nonvolatile storage system capable of reducing at least either the current supply amount or the fluctuations when breakdown is to be caused simultaneously in a plurality of memory cells.

The nonvolatile storage device includes: a memory cell array including a plurality of first signal lines, a plurality of second signal lines intersecting the plurality of first signal lines, and a plurality of memory cells disposed at intersection portions between the plurality of first signal lines and the plurality of second signal lines; and a plurality of switching elements that put ends of the respective first signal lines of the plurality of first signal lines and a power supply into either a connected state or a disconnected state, in which two or more switching elements among the plurality of switching elements can be in the connected state simultaneously at a time of writing into the memory cell.

A semiconductor device includes a semiconductor body having an active region and a substrate region that is disposed beneath the active region, and a bidirectional switch formed in the semiconductor body. The bidirectional switch includes first and second gate structures that are each configured to control a conductive state of an electrically conductive channel that is disposed in the active region, and first and second input-output terminals that are each in ohmic contact with the electrically conductive channel. A passive substrate voltage discharge circuit in parallel with the bidirectional switch is configured to discharge a voltage of the substrate region in both directions of the bidirectional switch. The passive substrate voltage discharge circuit includes first and second normally-on switches connected in anti-series between the first and second input-output terminals in a common source configuration with the substrate region as a midpoint.

A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.

An electrostatic discharge circuit and a display apparatus are discussed. The electrostatic discharge circuit can include a signal line configured to transmit a gate signal or a data signal, a first gate power voltage line, a second gate power voltage line, a first transistor and a second transistor disposed to overlap each other between the signal line and the second power voltage line, and a third transistor and a fourth transistor disposed to overlap each other between the signal line and the first power voltage line.

A protection device is provided for protecting an electrostatic discharge (ESD), sensitive device against an electromagnetic interference (EMI), event and/or an ESD event occurring on at least one of a first and second data line the ESD sensitive device is electrically connected to. Aspects of the present disclosure further relate to a system including an ESD sensitive device that is operatively coupled to a further device using a first and second data line, and the system includes the abovementioned protection device. The protection device uses a first inductor and/or second inductor and a first and/or shunt unit that each provide an electrical path between the first data line and/or second data line and ground in dependence of a voltage over the first and/or second inductor.

An ESD protection circuit is connected between a V.sub.DD terminal and a V.sub.SS terminal and is connected in parallel with an internal circuit which operates at an operating voltage and is damaged at a damage voltage or higher to protect the internal circuit from electrostatic discharge. The ESD protection circuit includes ESD protection elements connected in series. The ESD protection elements are transistors, diode elements, or a combination thereof. A sum of current-voltage characteristics of the ESD protection elements at a voltage higher than the operating voltage is higher than the operating voltage and lower than the damage voltage, until reaching a discharge current value or higher capable of protecting the internal circuit.

A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.

An ESD protection circuit includes a buffer circuit, a driving circuit, and a power-clamping circuit. The buffer circuit includes first and second transistors having a first conductivity type coupled in a cascade configuration between a first node and a first power supply node. A bonding pad is coupled to the first node. The drive circuit determines a state of at least one of the first and second transistors according to a control voltage. The drive circuit includes a third transistor having a second conductivity type, which is coupled between a second power supply node and a gate of the first transistor and is controlled by the control signal. The power-clamping circuit is coupled to the bonding pad and a gate of the third transistor at a second node. The control voltage is generated at the second node and determined by a voltage at the bonding pad.

This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.