A semiconductor device includes a semiconductor layer, a first region of a first conductivity type formed in the semiconductor layer and connected to a ground potential, a second region of a second conductivity type formed in the semiconductor layer, an insulating film formed on the semiconductor layer and covering the first region and the second region, an internal circuit, signal terminal for driving the internal circuit or to be driven by the internal circuit, a first wiring connecting the internal circuit and the signal terminal, a resistance element formed on the insulating film and interposed halfway through the first wiring, the resistance element including a first resistor facing the second region across the insulating film, and a second wiring connected to the first wiring on a side closer to the signal terminal than the resistance element and connecting the first wiring and the second region.

A nitride-based bidirectional switching device is provided for working with a battery protection controller having a power input terminal, a discharge over-current protection (DO) terminal, a charge over-current protection (CO) terminal, a voltage monitoring (VM) terminal and a ground terminal. The nitride-based bidirectional switching device comprises a nitride-based bidirectional switching element and an adaption module configured for receiving a DO signal and a CO signal from the battery protection controller and generating a main control signal for controlling the bidirectional switching element. By implementing the adaption circuit, the nitride-based bidirectional switching element can work with conventional battery protection controller for battery charging and discharging management. Therefore, a nitride-based battery management system can be realized with higher operation frequency as well as a more compact size.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an N-type well layer having a first positive N-type diffusion region coupled to an anode terminal; a P-type well layer having a second positive N-type diffusion region coupled to a cathode terminal; a substrate layer; a N-type buried layer provided between the P-type well layer and the substrate layer; and a dielectric layer coupled to a gate terminal. The N-type buried layer has a third N+ diffusion region coupled to a buried layer terminal. The N-type well layer is provided above the P-type well layer. A parasitic circuit is activated within the N-type well layer and the P-type well layer when the anode terminal receives a voltage equal or greater than a first threshold value.

An integrated power device includes a die containing a heterostructure with a main High Electron Mobility Transistor (HEMT) at least partly formed in the heterostructure and having a main source terminal, a main drain terminal and a main gate terminal. An overvoltage protection circuit is coupled between the main source terminal and the main gate terminal of the main HEMT. The overvoltage protection circuit includes at least one protection HEMT at least partly formed in the heterostructure.

A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.

An electrostatic discharge protection device is formed using only electrically connected transistors. The transistors include: a first MOS-type transistor forming a clamping circuit coupled between first and second supply nodes; a second MOS-type transistor coupled between the first supply node and a gate terminal of the first MOS-type transistor; and a third MOS-type transistor having a first gate terminal coupled to a gate terminal of the second MOS-type transistor, a second gate terminal coupled to one of the first and second supply nodes, and first and second conduction terminals coupled to the second supply node.

The present disclosure in various embodiments provides a hardened resist layer that can reduce resist scum defects in a resist layer. In one embodiment, a lithography method is provided. The method includes forming a resist layer over a substrate, performing an exposure process on the resist layer, performing a developing process on the resist layer to form a patterned resist layer having a plurality resist segments, exposing the patterned resist layer to a vacuum ultraviolet (VUV) radiation, and subjecting the resist pattern to a de-scum process.

A method includes forming first and second transistors over a substrate, the first and second transistors being parts of a buffer circuit in an input/output (I/O) circuit; forming a third transistor over the substrate and interposing between the first and second transistors from a cross-sectional view, the third transistor being a part of an electrostatic discharge (ESD) circuit in the I/O circuit; forming a first metal line horizontally extending from above the first transistor across the third transistor to above the second transistor, wherein the first metal line is electrically coupled to the first, second, and third transistors.

An electrostatic discharge circuit and a display apparatus are discussed. The electrostatic discharge circuit can include a signal line configured to transmit a gate signal or a data signal, a first gate power voltage line, a second gate power voltage line, a first transistor and a second transistor disposed to overlap each other between the signal line and the second power voltage line, and a third transistor and a fourth transistor disposed to overlap each other between the signal line and the first power voltage line.

The present disclosure generally relates to an electrostatic discharge (ESD) protection circuit in an integrated circuit and methods of forming such. In an example, an integrated circuit includes a transistor, a doped buried layer, and a capacitor. The transistor includes source and drain regions and a gate structure. The source and drain regions have a first conductivity type and are disposed in a semiconductor layer. The semiconductor layer has an opposite second conductivity type. The doped buried layer has the first conductivity type disposed in the semiconductor layer below the source and drain regions. The capacitor is disposed in the semiconductor layer and includes first and second capacitor electrodes extending to the doped buried layer. The first capacitor electrode electrically couples the drain region. The second capacitor electrode electrically couples the gate structure and conductively contacts the doped buried layer. The doped buried layer electrically couples the source region.