A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A source terminal is disposed on a first fin between a first dummy gate and a gate structure. A drain terminal is disposed on a second fin between a second dummy gate and a third dummy gate. A first gate oxide layer disposed under second and third dummy gates is made to be thinner than a second gate oxide layer disposed under the first dummy gate and the gate structure. By making the first gate oxide layer thinner, an overall footprint of the finFET device is reduced.

A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between it and electric field relaxation p-layer 16, low resistance n-layer 17 is provided. Low resistance n-layer 17 is formed deeper than trench T, and shallower than electric field relaxation p-layer 16, being connected to n.sup.-layer (drift layer) 12 just thereunder, and thus low resistance n-layer 17 and n.sup.-layer 12 are integrated to form a drift layer. Although low resistance n-layer 17 is n-type as is n.sup.-layer 12, donor concentration thereof is set higher than that of n.sup.-layer 12, thereby low resistance n-layer 17 having a resistivity lower than that of n.sup.-layer 12. This low resistance n-layer 17 is provided in on-current path (between electric field relaxation p-layer 16 and trench T), whereby low resistance n-layer 17 can lower the resistance to on-current.

A semiconductor arrangement is produced by providing a semiconductor carrier of a second conduction type and epitaxially growing a first semiconductor zone of a first conduction type on the carrier. The first semiconductor zone includes a semiconductor base material doped with first and second dopants which are made of different substances which are both different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes a decrease or an increase of a lattice constant of the first semiconductor zone. The second dopant causes one or both of hardening of the first semiconductor zone and an increase of the lattice constant of the first semiconductor zone if the first dopant causes a decrease, or a decrease of the lattice constant of the first semiconductor zone if the first dopant causes an increase.

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures.

A semiconductor device includes a first load contact, a second load contact and a semiconductor region positioned between the first and second load contacts. The semiconductor region includes: a first semiconductor contact zone in contact with the first load contact; a second semiconductor contact zone in contact with the second load contact; a first conductivity type semiconductor drift zone between the first and second semiconductor contact zones, wherein the semiconductor drift zone couples the first semiconductor contact zone to the second semiconductor contact zone. The semiconductor device further comprises: a trench comprising a control electrode and an insulator. The control electrode extends for at least 75% of the semiconductor drift zone. A drift zone doping concentration and an extension of the semiconductor drift zone defines a blocking voltage of the semiconductor device. The insulator is configured for insulating a voltage that amounts to at least 50% of said blocking voltage.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.