A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a pixel region with a pixel structure, an isolation region with an isolation structure disposed adjacent to the pixel region, and a contact pad region with a pad structure disposed adjacent to the isolation region. The pixel structure includes an epitaxial structure, which includes an embedded portion with a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure further includes a capping layer disposed on the protruding portion.

The quantum efficiency can be improved. A solid-state imaging device according to an embodiment includes: a plurality of pixels (110) arranged in a matrix, in which each of the pixels includes a first semiconductor layer (35), a photoelectric conversion section (PD1) disposed on the first semiconductor layer on a side of a first surface, an accumulation electrode (37) disposed on the first semiconductor layer close to a side of a second surface on a side opposite to the first surface, a wiring (61, 62, 63, 64) extending from the second surface of the first semiconductor layer, a floating diffusion region (FD1) connected to the first semiconductor layer via the wiring, and a first gate (11) that forms a potential barrier in a charge flow path from the first semiconductor layer to the floating diffusion region via the wiring.

A method for fabricating an integrated device, the method including: forming a first level including a first mono-crystal layer, where forming the first level includes forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of recessed channel transistors therein; disposing an overlying oxide on top of the first level; providing a second level including a second mono-crystal layer, where the second mono-crystal layer includes a plurality of image sensors; bonding the second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and including disposing a third level underneath the first level, where the third level includes a plurality of third transistors, and where the plurality of third transistors each include a single crystal channel.

An image sensor arrangement includes a first sensor layer having a first group of pixels. Each pixel of the first group includes a photodiode configured to detect electromagnetic radiation in a first wavelength range. The image sensor arrangement also includes a second sensor layer having a second group of pixels. Each pixel of the second group includes a photodiode configured to detect electromagnetic radiation in a second wavelength range. The image sensory arrangement further includes a readout layer having a readout circuit configured to read out electrical signals from the pixels of the first and the second group. The second sensor layer is arranged between the first sensor layer and the readout layer. The second wavelength range is outside a wavelength range detectable by the first sensor layer. The first sensor layer is attached to the second sensor layer by hybrid bonding.

Disclosed is a short-wave infrared spectrum detector, including: a photosensitive chip, including a plurality of detection pixels; a substrate; and a wavelength division component array, including a plurality of wavelength division pixels, each of the plurality of wavelength division pixels corresponding to a narrowband transmission spectrum, wherein the photosensitive chip and the wavelength division component array are monolithically integrated on both sides of the substrate, and an orthographic projection of each of the plurality of wavelength division pixels on the substrate covers an orthographic projection of at least one detection pixel on the substrate. The wavelength division structure and the photosensitive chip are integrated, so that each pixel has the ability of frequency-selective light spectrum detection, and a short-wave infrared spectrum detector integrated with wavelength division and detection is formed, realizing the miniaturization of the short-wave infrared spectral detection system.

A stacked focal planar array (FPA) device and method of fabrication. The method can include forming photodetectors or FPAs by heteroepitaxial growth of III-V PINs, APDs, or other photodetector devices that are bonded to a Si-based read-out integrated circuit (ROIC) wafer in a stacked configuration. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown on a first substrate using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and/or a selectively transparent buffer layer. And, silicon detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be bonded overlying the ROIC device in a flipped orientation and configured as pixels in a sensor array device coupled to the ROIC device.

A CMOS image sensor (CIS) device and a method for fabricating the CIS device are disclosed. The CIS device includes a stacked substrate structure including vertically bonded first and second pixel substrates and at least one visible-light pixel unit and at least one infrared light pixel unit that do not laterally overlap. The visible-light pixel unit includes a visible-light sensing element formed in the first pixel substrate, and the infrared light pixel unit includes an infrared light sensing element formed in the second pixel substrate. The visible-light sensing element and the infrared light sensing element are configured to sense visible and infrared light incident on a side of the first pixel substrate away from the second pixel substrate, respectively.

An infrared sensor includes a first semiconductor substrate, a second semiconductor substrate, a sealing frame, and a first connection. The first semiconductor substrate includes a first main surface and an infrared detection element. The second semiconductor substrate includes a second main surface and a signal processing circuit. The sealing frame surrounds an internal space with the first main surface, the infrared detection element, and the second main surface. The first connection electrically connects the infrared detection element and the signal processing circuit. The internal space is hermetically sealed by the first main surface, the infrared detection element, the second main surface, and the sealing frame. Each of the sealing frame and the first connection is sandwiched between the first main surface and the second main surface.