A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

A semiconductor device includes a silicon carbide layer having first and second surfaces, a first insulating film on the first surface, a first electrode on the first insulating film, a first silicon carbide region of a first conductivity type in the silicon carbide layer, a second silicon carbide region of a second conductivity type in the first silicon carbide region, a third silicon carbide region of the first conductivity type in the second silicon carbide region, a second electrode on the second surface, which contains metal, silicon, and carbon, and a third electrode in contact with the third silicon carbide region, which contains metal, silicon, and carbon, and has a carbon concentration higher than a carbon concentration of the second electrode.

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

A semiconductor device according to an embodiment includes a conductive region including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta), an n-type first SiC region, a p-type second SiC region provided between the conductive region and the n-type first SiC region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second SiC region, the n-type first SiC region, and the gate electrode.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

A power semiconductor device includes a semiconductor substrate, trench structures comprising a first, a second, a third and a fourth trench structure formed in the substrate, a second conductivity type body region formed between the trench structures, a first conductivity type source region formed in the second conductivity type body region, and an emitter electrode and a gate pad formed over the substrate, wherein each trench structure includes a top electrode and a bottom electrode, and each top electrode is insulated from the corresponding bottom electrode, and wherein the first trench structure is symmetric to the fourth trench structure, and the second trench structure is symmetric to the third trench structure, and wherein the first trench structure is not identical to the second trench structure, and wherein no first conductivity type source region is formed to be adjacent to the second trench structure and the third trench structure.

A method for producing a semiconductor device includes a first step of forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on sidewalls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film left as a sidewall around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a second gate insulating film around the pillar-shaped semiconductor layer and on the gate electrode and the gate line, removing a portion of the second gate insulating film on the gate line, depositing a second metal, etching back the second metal, removing the second gate insulating film on the pillar-shaped semiconductor layer, depositing a third metal, and etching a portion of the third metal and a portion of the second metal to form a first contact in which the second metal surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, a second contact that connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer, and a third contact made of the second metal and the third metal and formed on the gate line.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.