There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si.sub.3N.sub.4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO.sub.2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO.sub.2. The two SiO.sub.2 layers together form a blocking oxide layer.

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.

Integrated chips and methods of forming the same include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the second semiconductor fin is etched away. An extrinsic base is formed around the second semiconductor fin in a region exposed by etching away the gate stack.

A method is presented for forming a vertical field effect transistor (VFET) structure. The method includes forming a plurality of vertical fins over a substrate, forming a dummy gate between the plurality of vertical fins, removing the dummy gate with a subway etch to define a gate cavity, and forming a high-k metal gate (HKMG) stack within the gate cavity. The method further includes forming the first and second source/drain regions before the HKMG stack. The method further includes defining the HKMG stack by a replacement metal gate (RMG) process, the RMG process defined in part by the subway etch. The subway etch enables removal of the dummy gate from a side portion of the VFET structure.