Various embodiments of the present application are directed towards an integrated chip structure. The integrated chip structure includes a bottom electrode over a substrate, a top electrode over the bottom electrode, and a capacitor insulator structure between the bottom electrode and the top electrode. The capacitor insulator structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes a first dielectric material. The second dielectric layer includes a second dielectric material that is different than the first dielectric material. The second dielectric material is an amorphous solid. The third dielectric layer includes the first dielectric material.

An integrated circuit device comprising; a transistor on a substrate, and a capacitor structure electrically connected to the transistor. The capacitor structure includes a lower electrode, a lower interface film on the lower electrode, a capacitor dielectric film on the lower interface film, an upper interface film on the capacitor dielectric film, and an upper electrode on the upper interface film. The lower interface film includes a first lower interface layer including metal oxide doped with an impurity, a second lower interface layer including a material that is substantially the same as a material of the first lower interface layer and doped with nitrogen, and a third lower interface layer including a material that is identical to a material of the capacitor dielectric film and doped with nitrogen, the first to third lower interface layers being sequentially stacked on the lower electrode, and wherein the upper interface film includes a first upper interface layer including metal oxide, a second upper interface layer including a material that is identical to a material of the first upper interface layer and doped with nitrogen, and a third upper interface layer including a material that is identical to the material of the capacitor dielectric film and doped with nitrogen, the first to third upper interface layers being sequentially stacked on the upper electrode.

Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

A composite dielectric structure having one or more Leakage Blocking Layers (LBL) interleaved with one or more Laminate Dielectric Layers (LDL), Alloy Dielectric Layers (ADL), or Co-deposit Dielectric Layers (CDL). Each LDL, ADL, and CDL includes dopants incorporated in a respective base dielectric layer (BDL); where LDLs are formed by incorporating a doping layer into a BDL using a laminate method, ADLs are formed by incorporating a dopant into a BDL using an alloying method; and CDLs are formed by pulsing a BDL base material and a dopant together using a co-deposit method.

The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer.

The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide.

The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide.

The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.

A capacitance diode or variable capacitance diode includes first and second electrodes and a layer configuration disposed in contact-making fashion between the two electrodes. The layer configuration has, one after the other in a direction from the first electrode towards the second electrode, a layer formed of a ferroelectric material and an electrically insulating layer formed of a dielectric material having electrically charged defects. A method for producing a capacitance diode or a variable capacitance diode, a storage device and a detector including a capacitance diode or a variable capacitance diode are also provided.

A method of fabricating a pixel array includes forming a transistor network along a frontside of a semiconductor substrate. A contact element is formed for every pixel in the pixel array that is electrically coupled to a transistor within the transistor network. An interconnect layer is formed upon the frontside to control the transistor network with a dielectric that covers the contact element. A cavity is formed in the interconnect layer. A conductive layer is formed along cavity walls of the cavity and a dielectric layer is formed over the conductive layer within the cavity. A photosensitive semiconductor material is deposited over the dielectric layer within the cavity. An electrode cavity is formed that extends into the contact element. The electrode cavity is at least partially filled with a conductive material to form an electrode. The electrode, the conductive layer, and the photosensitive semiconductor material form a photosensitive capacitor.

A capacitor includes a first electrode including a first reinforcement material having a perovskite crystal structure; and a first metallic material having a perovskite crystal structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, wherein the first metallic material has greater a greater electronegativity than that of the first reinforcement material.

A method of manufacturing a multi-component thin film includes providing a substrate into a process chamber, performing a first cycle, the first cycle including forming a first atomic layer including a first precursor on the substrate by using an atomic layer deposition process, performing a third cycle, the third cycle including injecting an additive onto the first atomic layer, and performing a second cycle, the second cycle including forming a second atomic layer including a second precursor on the first atomic layer and the additive by using an atomic layer deposition process, wherein a thermal decomposition temperature of the additive is lower than each of a thermal decomposition temperature of the first precursor and a thermal decomposition temperature of the second precursor.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.