A capacitor is provided. The capacitor includes a first electrode, a second electrode disposed to face the first electrode, a dielectric layer of a rutile phase, disposed between the first electrode and the second electrode, and an interface layer between the first electrode and the dielectric layer, wherein the interface layer includes a first interface layer and a second interface layer, the first interface layer is adjacent to the first electrode, the second interface layer is adjacent to the dielectric layer, the first interface layer includes a conductive metal oxide having a work function in a range of about 4.8 eV to about 6.0 eV, the second interface layer includes a metal oxide having a rutile-phase crystal structure, and a thickness of the second interface layer is smaller than a thickness of the first interface layer.

A method of forming a semiconductor device includes forming a first electrode on a single-crystal structure. A dielectric layer is formed on the first electrode. A second electrode is formed on the dielectric layer. The forming a dielectric layer includes forming a first dielectric layer having a single-crystal perovskite structure on the first electrode, and forming a second dielectric layer on the first dielectric layer. An upper surface of the first dielectric layer adjacent to the second dielectric layer has a greater surface roughness than an upper surface of the second dielectric layer adjacent to the second electrode.

Disclosed are a capacitor dielectric layer, a manufacturing method therefor, and a capacitor structure. The capacitor dielectric layer includes any at least two stacked layers among a first stacked layer, a second stacked layer, and a third stacked layer, which are stacked along a first direction. Each stacked layer includes a first dielectric layer and a second dielectric layer. A main crystalline phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase, and a main crystalline phase of the second dielectric layer is at least one of the tetragonal structure phase and the orthorhombic structure phase. The capacitor dielectric layer has a high dielectric constant and low leakage current.

A capacitor component includes a support member; capacitance laminates laminated on one surface of the support member; at least one insulating layer disposed between the capacitance laminates; and a plurality of through structures each penetrating through at least one of the capacitance laminates. Each of the capacitance laminates includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers. One of the plurality of through structures includes a connection conductive pillar connected between first electrode layers of the capacitance laminates. Another of the plurality of through structures includes a first conductive pillar connected to a first electrode layer of one of the capacitance laminates, a dielectric through portion surrounding the first conductive pillar; and a through connection portion surrounding the dielectric through portion and connecting second electrode layers of the capacitance laminates to each other.

A semiconductor device includes a transistor disposed on a substrate; and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode; a dielectric layer structure disposed on the first electrode; and a second electrode disposed on the dielectric layer structure, the dielectric layer structure includes an interfacial layer disposed on the first electrode; a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material; an insertion layer disposed on the first dielectric layer; and a second dielectric layer disposed on the insertion layer and including a paraelectric material.

The present disclosure relates to an integrated chip including a ferroelectric layer. The ferroelectric layer includes a ferroelectric material. A first relaxation layer including a first material, different from the ferroelectric material, is on a first side of the ferroelectric layer. A second relaxation layer including a second material, different from the ferroelectric material, is on a second side of the ferroelectric layer, opposite the first side. A Young's modulus of the first relaxation layer is less than a Young's modulus of the ferroelectric layer.

A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes first dielectric layers and second dielectric layers interposed between the bottom electrode and the top electrode and are that are alternately stacked in the first direction. The first dielectric layers include a ferroelectric material, and the second dielectric layers include an anti-ferroelectric material. A lowermost second dielectric layer is interposed between a lowermost first dielectric layer and the bottom electrode, and an uppermost second dielectric layer is interposed between an uppermost first dielectric layer and the top electrode.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

A capacitor is provided. The capacitor includes a first electrode, a second electrode disposed to face the first electrode, a dielectric layer of a rutile phase, disposed between the first electrode and the second electrode, and an interface layer between the first electrode and the dielectric layer, wherein the interface layer includes a first interface layer and a second interface layer, the first interface layer is adjacent to the first electrode, the second interface layer is adjacent to the dielectric layer, the first interface layer includes a conductive metal oxide having a work function in a range of about 4.8 eV to about 6.0 eV, the second interface layer includes a metal oxide having a rutile-phase crystal structure, and a thickness of the second interface layer is smaller than a thickness of the first interface layer.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.