An electronic device having at least a first portion including a metal oxide that is in contact with a second portion including the said metal oxide, the first portion being semiconducting and the second portion being electrically insulating.

A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.

A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

A semiconductor device includes an insulating layer formed on a substrate, and a capacitor including first and second electrodes formed in the insulating layer, wherein a lower surface of the first electrode is formed to have a greater depth than a lower surface of the second electrode in the insulating layer.

An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.

Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.