SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

Claims

1. A method for fabricating a semiconductor device, comprising: providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region; forming a first fin-shaped structure on the MOSCAP region; forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region; removing the doped layer on the non-MOSCAP region; and performing an anneal process.

2. The method of claim 1, further comprising: forming a second fin-shaped structure on the non-MOSCAP region; forming the doped layer on the substrate and the second fin-shaped structure on the non-MOSCAP region; removing the doped layer on the non-MOSCAP region; forming a gate oxide layer on the non-MOSCAP region and the MOSCAP region; and performing the anneal process to drive dopants from the doped layer into the first fin-shaped structure.

3. The method of claim 1, wherein the non-MOSCAP region comprises an input/output (I/O) region and a low-voltage (LV) region.

4. The method of claim 1, further comprising performing the anneal process to form a maximum concentration of dopants at a surface of the first fin-shaped structure.

5. The method of claim 1, further comprising: performing the anneal process to form a first concentration of dopants at a surface of the first fin-shaped structure and a second concentration of dopants at a first depth of the first fin-shaped structure, wherein the second concentration is less than the first concentration.

6. The method of claim 5, wherein a decrease from the first concentration to the second concentration comprises an exponential decay.

7. The method of claim 1, wherein the doped layer comprises phosphosilicate glass (PSG).

8. A semiconductor device, comprising: a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region; a first fin-shaped structure on the MOSCAP region; a liner on the first fin-shaped structure; a gate oxide layer on the non-MOSCAP region and the MOSCAP region; and a gate electrode on the gate oxide layer.

9. The semiconductor device of claim 8, further comprising: a second fin-shaped structure on the non-MOSCAP region; the liner on the first fin-shaped structure; the gate oxide layer on the substrate and the second fin-shaped structure of the non-MOSCAP region and the liner of the MOSCAP region; and the gate electrode on the gate oxide layer.

10. The semiconductor device of claim 9, wherein a concentration of dopants in the first fin-shaped structure is greater than a concentration of dopants in the second fin-shaped structure.

11. The semiconductor device of claim 8, wherein the non-MOSCAP region comprises an input/output (I/O) region and a low-voltage (LV) region.

12. The semiconductor device of claim 8, further comprising a maximum concentration of dopants at a surface of the first fin-shaped structure.

13. The semiconductor device of claim 8, further comprising a first concentration of dopants at a surface of the first fin-shaped structure and a second concentration of dopants at a first depth of the first fin-shaped structure, wherein the second concentration is less than the first concentration.

14. The semiconductor device of claim 13, wherein a decrease from the first concentration to the second concentration comprises an exponential decay.

15. The semiconductor device of claim 8, wherein the first fin-shaped structure comprises phosphorus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1-6 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] FIG. 7 illustrates a concentration distribution on the non-MOSCAP region and MOSCAP region according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0009] Referring to FIGS. 1-6, FIGS. 1-6 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and two or more regions including a non-MOSCAP region 14 and a MOSCAP region 16 are defined on the substrate 12, in which the non-MOSCAP region 14 could be used for fabricating input/output (I/O) devices of low-voltage (LV) devices while the MOSCAP region 16 could be used for fabricating a MOSCAP device in the later process.

[0010] Next, a base 18 and fin-shaped structure 20 are formed on the non-MOSCAP region 14 and a plurality of fin-shaped structures 20 are formed on the substrate 12 of the MOSCAP region 16. Preferably, the fin-shaped structures 20 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.

[0011] Alternatively, the base 18 and the fin-shaped structures 20 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the base 18 and the fin-shaped structures 20. Moreover, the formation of the base 18 and the fin-shaped structures 20 could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12, and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding the base 18 and fin-shaped structures 20. These approaches for forming the base 18 and fin-shaped structures 20 are all within the scope of the present invention.

[0012] Next, a flowable chemical vapor deposition (FCVD) process is conducted to form an insulating layer (not shown) made of silicon oxide on the base 18 and the fin-shaped structures 20 and filling the trenches between the base 18 and the fin-shaped structures 20, and a planarizing process such as chemical mechanical polishing (CMP) process along with an etching process are conducted to remove part of the insulating layer for forming a shallow trench isolation 22.

[0013] Next, as shown in FIG. 2, a doped layer 24 is formed on the substrate 12 of the non-MOSCAP region 14 and MOSCAP region 16 to cover the base 18 and fin-shaped structures 20, and then a cap layer 26 is formed on the surface of the doped layer 24. In this embodiment, the doped layer 24 preferably includes phosphosilicate glass (PSG) and the cap layer 26 includes silicon oxide.

[0014] Next, as shown in FIG. 3, a photo-etching process is conducted by first forming a patterned mask (not shown) such as patterned resist on the MOSCAP region 16, and then conducting an etching process by using the patterned mask as mask to remove all of the cap layer 26 and doped layer 24 on the non-MOSCAP region 14 and even part of the cap layer 26 and doped layer 24 on the MOSCAP region 16 and expose the base 18 and fin-shaped structures 20 underneath. The patterned mask on the MOSCAP region 16 is then stripped thereafter.

[0015] Next, as shown in FIG. 4, an anneal process 28 is conducted to drive the dopants such as phosphorus in the doped layer 24 into the fin-shaped structure 20 for forming a doped region (not shown) and at the same time transforms the doped layer 24 into a non-doped liner 54 made of silicon oxide. The doped region now becomes a bottom electrode for the MOSCAP device. Next, the cap layer 26 and the liner 54 having no dopant remaining could be removed or not removed depending on the demand of the process.

[0016] Next, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) is conducted to form a gate oxide layer 30 made of silicon oxide on the substrate 12 and fin-shaped structures 20 on the non-MOSCAP region 14 and MOSCAP region 16. It should be noted that the gate oxide layer 30 on the non-MOSCAP region 14 is disposed directly on the surface of the substrate 12 and fin-shaped structure 20, the gate oxide layer 30 on the MOSCAP region 16 could be disposed directly on the surface of the cap layer 26 or fin-shaped structures 20 depending on whether the cap layer 26 and the liner 54 are removed.

[0017] Next, as shown in FIG. 5, gate electrodes 32, 34 are formed on the substrate 12 and fin-shaped structures 20 on the non-MOSCAP region 14 and MOSCAP region 16 respectively, in which the gate electrode 32 formed on the non-MOSCAP region 14 could be served as gate electrode for I/O device or LV device, the gate electrode 34 formed on the MOSCAP region 16 could be used as top electrode for the MOSCAP device, and the formation of the gate electrodes 32, 34 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process.

[0018] Since this embodiment pertains to a high-k last approach, a gate material layer 36 made of polysilicon and a selective hard mask (not shown) could be formed sequentially on the substrate 12, and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer 36 and part of the gate oxide layer 30 through single or multiple etching processes. After stripping the patterned resist, gate electrodes 32, 34 each made of a patterned material layer 36 is formed on the substrate 12 and fin-shaped structures 20 of the non-MOSCAP region 14 and MOSCAP region 16.

[0019] Next, at least a spacer (not shown) is formed on the sidewalls of the each of the gate electrodes 32, 34, a source/drain region (not shown) and/or epitaxial layer is formed in the fin-shaped structures 20 and/or substrate 12 adjacent to two sides of the spacer on the non-MOSCAP region 14, and selective silicide layers (not shown) could be formed on the surface of the source/drain region. In this embodiment, the spacer could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO.sub.2, SiN, SION, SiCN, or combination thereof. The source/drain region could include n-type dopants or p-type dopants depending on the type of device being fabricated.

[0020] Next, an interlayer dielectric (ILD) layer 38 is formed on the gate electrodes 32, 34 and a planarizing process such as CMP is conducted to remove part of the ILD layer 38 for exposing the gate material layers 36 or gate electrodes 32, 34 made of polysilicon so that the top surface of the gate electrodes 32, 34 are even with the top surface of the ILD layer 38.

[0021] Next, as shown in FIG. 6, a replacement metal gate (RMG) process is conducted to transform the gate electrodes 32, 34 on the non-MOSCAP region 14 and MOSCAP region 16 into metal gates 56. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH.sub.4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 36 and even gate oxide layer 30 for forming recesses (not shown) in the ILD layer 38.

[0022] Next, a selective interfacial layer (not shown) or gate dielectric layer, a high-k dielectric layer 46, a work function metal layer 48, and a low resistance metal layer 50 are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer 50, part of work function metal layer 48, and part of high-k dielectric layer 46 to form metal gates 56. In this embodiment, the gate structures or metal gates 56 fabricated through high-k last process of a gate last process preferably includes an interfacial layer or gate oxide layer 30, a U-shaped high-k dielectric layer 46, a U-shaped work function metal layer 48, and a low resistance metal layer 50.

[0023] In this embodiment, the high-k dielectric layer 46 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 50 may be selected from hafnium oxide (HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), yttrium oxide (Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium titanate oxide (SrTiO.sub.3), zirconium silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO.sub.4), strontium bismuth tantalate (SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT), barium strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST) or a combination thereof.

[0024] In this embodiment, the work function metal layer 48 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer 48 having a work function ranging between 3.9 cV and 4.3 V may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAI), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAIC), but it is not limited thereto. For a PMOS transistor, the work function metal layer 48 having a work function ranging between 4.8 eV and 5.2 cV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer 48 and the low resistance metal layer 50, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 50 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

[0025] Next, part of the high-k dielectric layer 46, part of the work function metal layer 48, and part of the low resistance metal layer 50 are removed to form recesses (not shown), and a hard mask 52 is formed into each of the recesses so that the top surfaces of the hard masks 52 and the ILD layer 38 are coplanar. Preferably the hard masks 52 could include SiO.sub.2. SiN, SiON, SiCN, or combination thereof.

[0026] Next, a photo-etching process is conducted by using a patterned mask (not shown) as mask to remove part of the ILD layer 38 adjacent to the gate electrode 32 on the non-MOSCAP region 14 for forming contact holes (not shown) exposing the source/drain region underneath. Next, conductive materials including a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and a metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs (not shown) electrically connecting the source/drain region. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0027] Referring again to FIGS. 6-7, FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention and FIG. 7 illustrates a concentration distribution on the non-MOSCAP region 14 and MOSCAP region 16 according to an embodiment of the present invention. As shown in FIG. 6, the semiconductor device includes a substrate 12 having a non-MOSCAP region 14 and a MOSCAP region 16, a MOS transistor disposed on the non-MOSCAP region 14, and a MOSCAP device disposed on the MOSCAP region 16. In this embodiment, the MOSCAP device includes a plurality of fin-shaped structures 20 disposed on the substrate 12, at least an insulating layer such as a combination of the gate oxide layer 30 and/or high-k dielectric layer 46 on the fin-shaped structures 20, and a gate electrode 34 disposed on the gate oxide layer 30. Preferably, the heavily doped fin-shaped structures 20 are served as a bottom electrode for the MOSCAP device, dielectric layers including the gate oxide layer 30 and/or high-k dielectric layer 46 are used as a capacitor dielectric layer for the MOSCAP device, and the gate electrode 34 is served as a top electrode for the MOSCAP device.

[0028] Despite the fin-shaped structures 20 on the non-MOSCAP region 14 and MOSCAP region 16 are fabricated through same process, the overall and/or maximum doping concentrations of the fin-shaped structures 20 on the non-MOSCAP region 14 however are both less than overall and/or maximum doping concentrations of the fin-shaped structures 20 on the MOSCAP region 16. Referring to FIG. 7, FIG. 7 illustrates a concentration distribution within the fin-shaped structures 20 on the non-MOSCAP region and MOSCAP region 16, in which X-axis depicts the depth of the fin-shaped structures while Y-axis depicts concentration of dopants within the fin-shaped structures. As shown in FIG. 7, since the non-MOSCAP region 14 (represented by dotted line) typically involves employing standard ion implantation process to implant dopants into the fin-shaped structures 20, the concentration of dopants at surface of the fin-shaped structures 20 is less than the concentration at a first depth but greater than the concentration at a second depth as the first depth is less than the second depth. For instance, the concentration of dopants at surface of the fin-shaped structures 20 on the non-MOSCAP region 14 or at depth 0 nm is slightly less than 1.010.sup.20 atoms/cm.sup.3 or most preferably between 7.010.sup.19 atoms/cm.sup.3 to 9.010.sup.19 atoms/cm.sup.3, the concentration of dopants at depth 20 nm is slightly greater than 1.010.sup.20 atoms/cm.sup.3 or most between 2.010.sup.20 atoms/cm.sup.3 to 5.010.sup.20 atoms/cm.sup.3, and the concentration of dopants at depth 50 nm is between 8.010.sup.17 atoms/cm.sup.3 to 2.010.sup.18 atoms/cm.sup.3.

[0029] In the MOSCAP region 16 since the dopants are driven into the fin-shaped structures 20 through SSD technique according to aforementioned embodiment and in contrast to the maximum concentration of the fin-shaped structures 20 on the non-MOSCAP region 14 appears at a depth lower than the surface of the fin-shaped structures 20, the maximum concentration of the fin-shaped structures 20 on the MOSCAP region 16 is at the surface of the fin-shaped structures 20. For instance, the concentration of dopants at surface of the fin-shaped structures 20 on the MOSCAP region 16 or at depth 0 nm is substantially equal to 5.010.sup.20 atoms/cm.sup.3 or most preferably between 3.010.sup.20 atoms/cm.sup.3 to 6.010.sup.20 atoms/cm.sup.3 while the concentration of dopants at depth 50 nm is between 8.010.sup.17 atoms/cm.sup.3 to 2.010.sup.18 atoms/cm.sup.3. In this embodiment, the concentration slope of the non-MOSCAP region 14 is slightly less than the concentration slope of the MOSCAP region 16 and a decrease from the maximum concentration to any concentration less than the maximum concentration on the MOSCAP region 16 is preferably shown by a much more steep drop such as an exponential decay.

[0030] Overall, the present invention discloses an approach of using SSD technique for fabricating MOSCAP device, which first forms multiple fin-shaped structures on a substrate of MOSCAP region, forms a doped layer on the substrate of the non-MOSCAP region and fin-shaped structures on the MOSCAP region, removes all the doped layer on the non-MOSCAP region, and then conducts a thermal treatment or anneal process to drive the dopants from the doped layer into the fin-shaped structures on the MOSCAP region. By using this approach to fabricate MOSCAP device, the maximum concentration of dopants in the fin-shaped structures on the MOSCAP region 16 would appear at the surface of the fin-shaped structures while the maximum concentration of dopants in the fin-shaped structures on the non-MOSCAP region 14 would appear at a depth lower than the surface of the fin-shaped structure.

[0031] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.