A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.

A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode.

A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

A thin-film transistor (TFT) array substrate includes a transistor disposed on a base substrate and a storage capacitor electrically connected to the transistor. The transistor includes a gate electrode, an active layer electrically insulated from the gate electrode, the active layer including a semiconductor material, and a first electrode and a second electrode disposed to be spaced apart from each other on the active layer. The storage capacitor includes a lower electrode including a light inflow path, and an upper electrode disposed to face the lower electrode and electrically connected to the second electrode.

ALD of Hf.sub.xAl.sub.yC.sub.z films using hafnium chloride (HfCl.sub.4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl.sub.4 pulse time allows for control of the Al % incorporation in the Hf.sub.xAl.sub.yC.sub.z film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the Hf.sub.xAl.sub.yC.sub.z work function layer coupled with ALD deposited HfO.sub.2 high-k gate dielectric layers was quantified to be mid-gap at 4.6 eV. Thus, Hf.sub.xAl.sub.yC.sub.z is a promising metal gate work function material allowing for the tuning of device threshold voltages (V.sub.th) for anticipated multi-V.sub.th integrated circuit (IC) devices.

An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.