A high-density capacitor and a method for manufacturing the same are disclosed. The high-density capacitor includes a metal-oxide-semiconductor (MOS) capacitor having a silicon layer with a dopant concentration of at least 11020 cm-3; a first dielectric layer formed on above the silicon layer, and a first metal layer formed above the first dielectric layer.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.

A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.

A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200 C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistor can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage.