A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Devices, systems, and methods for ion trapping with integrated electromagnets are described herein. One device includes a plurality of electrodes configured to trap an ion above a surface of the device, a medial coil and a plurality of peripheral coils, each positioned at a respective radial angle associated with the medial coil, wherein the medial coil is configured to generate a first magnetic field having a first orientation, and wherein the peripheral coils are configured to generate a second magnetic field having a second orientation that opposes the first orientation.

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

A semiconductor device includes a semiconductor substrate having a first region and a second region; a first planar type capacitor including a gate electrode which is positioned in any one region of the first region and the second region; a non-planar type capacitor including a plurality of non-planar type electrodes which are positioned in the other region of the first region and the second region; a second planar type capacitor including a planar type electrode which is positioned over the first planar type capacitor to overlap with the first planar type capacitor; and a common node under the non-planar type capacitor.

Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures.

An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.