Semiconductor device with temperature-detecting diode

Abstract

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

Claims

1. A semiconductor device comprising: an insulated gate semiconductor element that makes a current flow in a thickness direction of a semiconductor substrate; a temperature detecting diode that detects a temperature of the insulated gate semiconductor element and is provided in an active region of the insulated gate semiconductor element; an anode metal wiring line that is provided on a first main surface side of the semiconductor substrate and is connected to an anode of the temperature detecting diode; a cathode metal wiring line that is provided on the first main surface side of the semiconductor substrate and is connected to a cathode of the temperature detecting diode; a first insulating film that is formed on a first main surface of the semiconductor substrate between the anode and cathode metal wiring lines and the semiconductor substrate; a first conductive layer that is formed on the first insulating film; a second insulating film that is formed on the first conductive layer; a first semiconductor layer that is formed between the second insulating film and the anode metal wiring line; an interlayer insulating film that is formed between the first semiconductor layer and the anode metal wiring line; a second semiconductor layer that is formed between the second insulating film and the cathode metal wiring line, the interlayer insulating film being formed between the second semiconductor layer and the cathode metal wiring line; a second conductive layer that is formed on the first insulating film, the second insulating film being formed on the second conductive layer; a first capacitor that has the second insulating film between the first semiconductor layer and the first conductive layer as a first capacitive component region; a second capacitor that has the second insulating film between the second semiconductor layer and the first conductive layer as a second capacitive component region; and a third capacitor that has the first insulating film between the first conductive layer and the semiconductor substrate as a third capacitive component region, wherein the first semiconductor layer and the anode metal wiring line are electrically insulated, while the second semiconductor layer and the cathode metal wiring line are electrically insulated, the first conductive layer and the second conductive layer are electrically connected to a gate electrode of the insulated gate semiconductor element, and the second conductive layer is provided between the temperature detecting diode and the first conductive layer, and the active region.

2. The semiconductor device according to claim 1, wherein the insulated gate semiconductor element includes: a first semiconductor region of a first conductivity type that is formed in a surface layer on the first main surface side of the semiconductor substrate; a second semiconductor region of a second conductivity type that is formed in a surface layer of the first semiconductor region which is close to the first main surface; a trench that extends from a surface of the selectively formed second semiconductor region to the first semiconductor region; a gate insulating film that is formed along a surface of the first semiconductor region and along an inner wall of the trench in the trench, the gate electrode being provided in the trench so as to come into contact with the gate insulating film; and a third semiconductor region of the first conductivity type that is adjacent to a side wall of the trench and the gate insulating film, and the interlayer insulating film is formed on the first main surface side of the gate electrode.

3. The semiconductor device according to claim 1, wherein the temperature detecting diode includes: the first insulating film that is formed on the first main surface of the semiconductor substrate; a third conductive layer that is formed on the first insulating film, the second insulating film being formed on the third conductive layer; a first-conductivity-type layer and a second-conductivity-type layer that are formed on the second insulating film; a fourth capacitor that has the second insulating film between the third conductive layer and the first-conductivity-type layer as a fourth capacitive component region; a fifth capacitor that has the second insulating film between the third conductive layer and the second-conductivity-type layer as a fifth capacitive component region; and a sixth capacitor that has the first insulating film between the third conductive layer and the semiconductor substrate as a sixth capacitive component region, wherein the third conductive layer is electrically insulated from the first conductive layer and the second conductive layer.

4. The semiconductor device according to claim 2, wherein the first insulating film and the gate insulating film are each a portion, formed at a same time, of a same insulating film.

5. The semiconductor device according to claim 3, wherein the first conductive layer, the second conductive layer, and the third conductive layer are each a portion, formed at a same time, of a same conductive layer.

6. A semiconductor device comprising: an insulated gate semiconductor element that makes a current flow in a thickness direction of a semiconductor substrate; a temperature detecting diode that detects a temperature of the insulated gate semiconductor element and is provided in an active region of the insulated gate semiconductor element; an anode metal wiring line that is provided on a first main surface side of the semiconductor substrate and is connected to an anode of the temperature detecting diode; a cathode metal wiring line that is provided on the first main surface side of the semiconductor substrate and is connected to a cathode of the temperature detecting diode; a first insulating film that is formed on a first main surface of the semiconductor substrate between the anode and cathode metal wiring lines and the semiconductor substrate; a first conductive layer that is formed on the first insulating film; a second insulating film that is formed on the first conductive layer; an interlayer insulating film that is formed between the second insulating film and the anode metal wiring line, the interlayer insulating film being formed between the second insulating film and the cathode metal wiring line; a second conductive layer that is formed on the first insulating film, the second insulating film being formed on the second conductive layer; and a first capacitor that has the first insulating film between the first conductive layer and the semiconductor substrate as a first capacitive component region, wherein the first conductive layer and the anode metal wiring line are electrically insulated, while the first conductive layer and the cathode metal wiring line are electrically insulated, the first conductive layer and the second conductive layer are electrically connected to a gate electrode of the insulated gate semiconductor element, and the second conductive layer is formed between the temperature detecting diode and the first conductive layer, and the active region.

7. The semiconductor device according to claim 6, wherein the insulated gate semiconductor element includes: a first semiconductor region of a first conductivity type that is formed in a surface layer on the first main surface side of the semiconductor substrate; a second semiconductor region of a second conductivity type that is formed in a surface layer of the first semiconductor region that is close to the first main surface; a trench that extends from a surface of the selectively formed second semiconductor region to the first semiconductor region; a gate insulating film that is formed along a surface of the first semiconductor region and along an inner wall of the trench in the trench, the gate electrode being provided in the trench so as to come into contact with the gate insulating film; and a third semiconductor region of the first conductivity type that is adjacent to a side wall of the trench and the gate insulating film, and the interlayer insulating film is formed on the first main surface side of the gate electrode.

8. The semiconductor device according to claim 6, wherein the temperature detecting diode includes: the first insulating film that is formed on the first main surface of the semiconductor substrate; a third conductive layer that is formed on the first insulating film, the second insulating film being formed on the third conductive layer; a first-conductivity-type layer and a second-conductivity-type layer that are formed on the second insulating film; a second capacitor that has the second insulating film between the third conductive layer and the first-conductivity-type layer as a second capacitive component region; a third capacitor that has the second insulating film between the third conductive layer and the second-conductivity-type layer as a third capacitive component region; and a fourth capacitor that has the first insulating film between the third conductive layer and the semiconductor substrate as a fourth capacitive component region, wherein the third conductive layer is electrically insulated from the first conductive layer and the second conductive layer.

9. The semiconductor device according to claim 7, wherein the first insulating film and the gate insulating film are each a portion, formed at a same time, of a same insulating film.

10. The semiconductor device according to claim 8, wherein the first conductive layer, the second conductive layer, and the third conductive layer are each a portion, formed at a same time, of a same conductive layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating the structure of a semiconductor device according to Embodiment 1 of the invention;

(2) FIG. 2 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 2 of the invention;

(3) FIG. 3 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 2 of the invention;

(4) FIG. 4 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 2 of the invention;

(5) FIG. 5 is a diagram illustrating the structure of a semiconductor device according to Embodiment 3 of the invention;

(6) FIG. 6 is a diagram illustrating the structure of a semiconductor device according to Embodiment 4 of the invention;

(7) FIG. 7 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 5 of the invention;

(8) FIG. 8 is a cross-sectional view illustrating another example of the structure of the semiconductor device according to Embodiment 5 of the invention;

(9) FIG. 9 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 6 of the invention;

(10) FIG. 10 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 6 of the invention;

(11) FIG. 11 is a diagram illustrating the structure of a semiconductor device according to Embodiment 7 of the invention;

(12) FIG. 12 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 8 of the invention;

(13) FIG. 13 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 8 of the invention;

(14) FIG. 14 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 8 of the invention;

(15) FIG. 15 is a diagram illustrating the structure of a semiconductor device according to Embodiment 9 of the invention;

(16) FIG. 16 is a diagram illustrating the structure of a semiconductor device according to Embodiment 10 of the invention;

(17) FIG. 17 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 11 of the invention;

(18) FIG. 18 is a cross-sectional view illustrating a method for producing a semiconductor device according to Embodiment 12 of the invention;

(19) FIG. 19 is a cross-sectional view illustrating a method for producing a semiconductor device according to Embodiment 13 of the invention;

(20) FIG. 20 is a plan view illustrating the structure of a MOS semiconductor device according to the related art; and

(21) FIG. 21 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line A-A of FIG. 20.

(22) FIG. 22 is a diagram illustrating the structure of a semiconductor device according to Embodiment 14 of the invention.

(23) FIG. 23 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 14 of the invention.

(24) FIG. 24 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 14 of the invention.

(25) FIG. 25 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 14 of the invention.

(26) FIG. 26 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 14 of the invention.

(27) FIG. 27 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 14 of the invention.

(28) FIG. 28 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 14 of the invention.

(29) FIG. 29 is a cross-sectional view illustrating the structure of a semiconductor device according to Embodiment 15 of the invention.

(30) FIG. 30 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 15 of the invention.

(31) FIG. 31 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 15 of the invention.

(32) FIG. 32 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 15 of the invention.

DETAILED DESCRIPTION

(33) Hereinafter, various non-limiting embodiments of a semiconductor device and a method for producing the same according to the invention will be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, in the layers or regions having n or p appended thereto, an electron or a hole means a majority carrier. In addition, symbols + and added to n or p mean that impurity concentration is higher and lower than that of the layer without the symbols. In the description of the following embodiment and the accompanying drawings, the same components are denoted by the same reference numerals and the description thereof will not be repeated.

(34) In each of the following embodiments, a MOSFET (insulated gate field effect transistor) is used as a MOS semiconductor element. However, the MOS semiconductor element is not limited to the MOSFET. For example, an insulated gate bipolar transistor (IGBT) can be used as the MOS semiconductor element.

(35) A temperature detecting diode and a protective diode described in the claims indicate a temperature detecting diode 1 and a protective diode 2, respectively.

(36) Embodiment 1

(37) A semiconductor device according to Embodiment 1 of the invention will be described. FIG. 1 is a diagram illustrating the structure of the semiconductor device according to Embodiment 1 of the invention. FIG. 1(A) is a plan view illustrating the structure of the semiconductor device according to Embodiment 1 of the invention and FIG. 1(B) is an equivalent circuit diagram illustrating protective diodes 21 and 22 illustrated in FIG. 1(a).

(38) As illustrated in FIGS. 1(a) and 1(b), the semiconductor device according to Embodiment 1 includes a MOSFET 51, a temperature detecting diode 1, and the protective diodes 21 and 22 (protective diode 2). The temperature detecting diode 1 has a function of detecting the temperature of the MOSFET 51. The protective diode 21 is connected between a gate G and a source S of the MOSFET 51 and has a function of preventing dielectric breakdown due to, for example, static electricity or surge (transient overvoltage). The protective diode 22 is connected between the gate G and a drain D of the MOSFET 51 and has a function of preventing the breakdown of the element due to, for example, static electricity or surge.

(39) The temperature detecting diode 1 is formed in the vicinity of a central portion of an active region 8 of the MOSFET 51 in which the temperature is at the highest. A source electrode 34 (source S) of the MOSFET 51 is arranged so as to cover a portion of the active region 8 other than the temperature detecting diode 1, an anode metal wiring line 6, and a cathode metal wiring line 7. An anode electrode pad 3 that is connected to an anode A of the temperature detecting diode 1, a cathode electrode pad 4 that is connected to a cathode K of the temperature detecting diode 1, and a gate electrode pad 5 that is connected to the gate G of the MOSFET 51 are formed in an outer circumferential portion of the active region 8. The anode electrode pad 3, the cathode electrode pad 4, and the gate electrode pad 5 are arranged along, for example, the outer circumference of the active region 8. A drain electrode 35 (drain D) of the MOSFET 51 is arranged closer to the outer circumference of the semiconductor device than the gate electrode pad 5.

(40) The temperature detecting diode 1 is arranged so as to be separated from the anode electrode pad 3 and the cathode electrode pad 4. The anode A (FIG. 1(B)) of the temperature detecting diode 1 and the anode electrode pad 3 are connected to each other by the anode metal wiring line 6. The cathode K of the temperature detecting diode 1 and the cathode electrode pad 4 are connected to each other by the cathode metal wiring line 7. The anode metal wiring line 6 and the cathode metal wiring line 7 extend from the temperature detecting diode 1 to the anode electrode pad 3 and the cathode electrode pad 4 along, for example, the outer circumference of the active region 8, respectively. The protective diode 21 is formed on the side of the gate electrode pad 5 close to the inside of the semiconductor device (the central portion side of the active region 8) along the gate electrode pad 5, the anode electrode pad 3, and the cathode electrode pad 4 and is connected to the gate electrode pad 5 and the source electrode 34.

(41) The protective diode 22 is formed on the side of the gate electrode pad 5 close to the outer circumference of the semiconductor device and is connected to the gate electrode pad 5 and the drain electrode 35. A semiconductor layer and a capacitive component region (not illustrated) which is provided so as to come into contact with the lower surface of the semiconductor layer (a semiconductor-substrate-side surface (not illustrated)) and improves the static electricity resistance of the temperature detecting diode 1 are formed in a portion below the anode metal wiring line 6 (a portion that is arranged closer to the semiconductor substrate than the anode metal wiring line 6 in the depth direction of the plane of paper) and in a portion below the cathode metal wiring line 7 (a portion closer to the semiconductor substrate than the cathode metal wiring line 7).

(42) A capacitive component region (not illustrated) is also formed in a portion (a portion closer to the semiconductor substrate than the temperature detecting diode 1) below temperature detecting diode 1 and in a portion (a portion closer to the semiconductor substrate than the protective diodes 21 and 22) below the protective diodes 21 and 22. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode 1 and the protective diodes 21 and 22, without reducing the area of the active region 8. The temperature detecting diode 1 and the protective diodes 21 and 22 may be independently formed according to the purpose of use or they may be combined with each other.

(43) As described above, according to Embodiment 1, the capacitive component region is formed below the anode metal wiring line 6 that connects the temperature detecting diode 1 and the anode electrode pad 3 and below the cathode metal wiring line 7 that connects the temperature detecting diode 1 and the cathode electrode pad 4. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode 1. In addition, according to Embodiment 1, the capacitive component region is formed below the temperature detecting diode 1 and the protective diodes 21 and 22. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode 1 and the protective diodes 21 and 22, without reducing the area of the active region 8.

(44) Embodiment 2

(45) The temperature detecting diode 1, the anode metal wiring line 6, and the cathode metal wiring line 7 according to Embodiment 1 will be described in detail as a semiconductor device according to Embodiment 2 of the invention. FIGS. 2 and 4 are cross-sectional views illustrating the structure of the semiconductor device according to Embodiment 2 of the invention. FIG. 3 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 2 of the invention. The planar structure of the semiconductor device according to Embodiment 2 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line A-A of FIG. 1(A). FIG. 3 is an equivalent circuit diagram of FIG. 2. FIG. 4 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line B-B of FIG. 1(A).

(46) As illustrated in FIGS. 2 to 4, in the semiconductor device according to Embodiment 2, an n first semiconductor layer 9, which will be a drift region of the MOSFET 51, is formed on the first main surface side of a semiconductor substrate 100. A p-type first semiconductor region 10, which will be a base region of the MOSFET 51, is formed in a surface layer (a surface layer close to the first main surface of the substrate; hereinafter, simply referred to as a surface layer) of the first semiconductor layer 9. An n.sup.+ drain region 38 is formed on the second main surface side of the semiconductor substrate 100. A drain electrode 37 is formed on the surface of the drain region 38 (the second main surface of the semiconductor substrate 100).

(47) A trench 31 is formed in the active region 8 in which a current flows when the semiconductor device is turned on so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. A gate insulating film 32 is formed in the trench 31 along the inner wall of the trench 31. A gate electrode 33 is provided in the trench 31, with the gate insulating film 32 interposed therebetween. The gate insulating film 32 is an oxide film. The gate electrode 33 is covered with an interlayer insulating film 17 which is made of polysilicon doped with impurities (for example, n-type impurities). An n.sup.+ second semiconductor region 11, which will be a source region, is formed adjacent to the side wall of the trench 31. A source electrode 34 comes into contact (electrical contact) with the second semiconductor region 11 and the first semiconductor region 10.

(48) A first insulating film 12 is formed on the first semiconductor region 10 (that is, on the first main surface of the semiconductor substrate 100) in a portion (a portion which is closer to the semiconductor substrate 100 than the temperature detecting diode 1) below the temperature detecting diode 1. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage. An n.sup.+ conductive layer 14 which is made of polysilicon doped with impurities is formed on the upper surface (the surface opposite to the semiconductor substrate 100) of the first insulating film 12. A second insulating film 13 is formed on the upper surface of the conductive layer 14. The temperature detecting diode 1 which is made of polysilicon is formed on the upper surface of the second insulating film 13. The second insulating film 13 is an oxide film. The thickness of the second insulating film 13 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, electrostatic or overvoltage.

(49) The temperature detecting diode 1 is formed by connecting a plurality of zener diodes, each including a p.sup.+ layer 111 and an n.sup.+ layer 112, in series to each other. The p.sup.+ layer 111 is made of, for example, polysilicon doped with boron (B). The n.sup.+ layer 112 is made of, for example, polysilicon doped with arsenic (As) or phosphorus (P).

(50) The anode metal wiring line 6 connects the temperature detecting diode 1 and the anode electrode pad 3. In a portion (a portion which is closer to the semiconductor substrate 100 than the anode metal wiring line 6) below the anode metal wiring line 6, the first insulating film 12, which is an oxide film having a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the first semiconductor region 10. The conductive layer 14 which is made of polysilicon is formed on the upper surface of the first insulating film 12. The second insulating film 13, which is an oxide film having a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the upper surface of the conductive layer 14. A first semiconductor layer 15 is formed on the upper surface of the second insulating film 13.

(51) The cathode metal wiring line 7 connects the temperature detecting diode 1 and the cathode electrode pad 4. In a portion (a portion which is closer to the semiconductor substrate 100 than the cathode metal wiring line 7) below the cathode metal wiring line 7, the first having a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the first semiconductor region 10. The conductive layer 14 which is made of polysilicon is formed on the upper surface of the first insulating film 12. The second insulating film 13, which is an oxide film having a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the upper surface of the conductive layer 14. A second semiconductor layer 16 is formed on the upper surface of the second insulating film 13.

(52) The first semiconductor layer 15 and the second semiconductor layer 16 are made of polysilicon doped with impurities. The thickness of the first semiconductor layer 15 and the second semiconductor layer 16 is in the range of, for example, about 0.5 m to 1 m. The formation of polysilicon, ion implantation, and thermal diffusion for forming the first semiconductor layer 15 and the second semiconductor layer 16 are performed in the same step as the formation of the temperature detecting diode 1. The conductivity type of the first semiconductor layer 15 and the second semiconductor layer 16 may be a p type or an n type. When polysilicon is, for example, a p type, boron can be used as the impurities added to polysilicon. When polysilicon is an n type, arsenic or phosphorus can be used as the impurities.

(53) The first semiconductor layer 15 below the anode metal wiring line 6 and the second semiconductor layer 16 below the cathode metal wiring line 7 are formed on the same first semiconductor region 10, the same first insulating film 12, the same conductive layer 14, and the same second insulating film 13.

(54) The temperature detecting diode 1, the first semiconductor layer 15 below the anode metal wiring line 6, and the second semiconductor layer 16 below the cathode metal wiring line 7 are formed on the same first semiconductor region 10, the same first insulating film 12, the same conductive layer 14, and the same second insulating film 13.

(55) The conductive layer 14 is made of, for example, polysilicon doped with n-type impurities at an impurity concentration of 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3. For example, the conductive layer 14 is formed at the same time as the gate electrode 33 provided in the trench 31. Therefore, the conductive layer 14 may have a thickness required to fill the trench 31. In Embodiment 2 of the invention, the thickness of the conductive layer 14 may be, for example, about 0.5 m.

(56) The conductive layer 14 is electrically insulated from the gate electrode 33, the source electrode 34, the drain electrode 35, the anode electrode, and the cathode electrode by the interlayer insulating film 17 and the second insulating film 13. In this way, it is possible to prevent the adverse effect of a surge voltage applied to each electrode on the conductive layer 14.

(57) As such, the first insulating film 12, the conductive layer 14, and the second insulating film 13 are formed on the first semiconductor region 10 and the temperature detecting diode 1 is provided on the upper surface of the second insulating film 13. Therefore, it is possible to form a capacitor C2 (C2a to C2j) which has the second insulating film 13 between the temperature detecting diode 1 and the conductive layer 14 as the capacitive component region. In addition, it is possible to form a capacitor C1 (C1a to C1e) which has the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10 as the capacitive component region.

(58) The first insulating film 12, the conductive layer 14, and the second insulating film 13 are formed on the first semiconductor region 10 and the first semiconductor layer 15 is provided on the upper surface of the second insulating film 13. Therefore, it is possible to form a capacitor C4 which has, as the capacitive component region, the second insulating film 13 provided between the conductive layer 14 and the first semiconductor layer 15 below the anode metal wiring line 6. In addition, the first insulating film 12, the conductive layer 14, and the second insulating film 13 are formed on the first semiconductor region 10 and the second semiconductor layer 16 is provided on the upper surface of the second insulating film 13. Therefore, it is possible to form a capacitor C5 which has, as the capacitive component region, the second insulating film 13 provided between the conductive layer 14 and the second semiconductor layer 16 below the cathode metal wiring line 7. In addition, it is possible to form a capacitor C3 which has the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10 as the capacitive component region.

(59) In order to form the capacitor C4 and the capacitor C5 which have the second insulating film 13 as the capacitive component region, the anode metal wiring line 6 and the cathode metal wiring line 7 can be directly formed on the upper surface of the second insulating film 13, without forming the first semiconductor layer 15 and the second semiconductor layer 16. However, this structure is not preferable for the following reason. Before the anode metal wiring line 6 and the cathode metal wiring line 7 are formed, a step of covering the first main surface of the semiconductor substrate 100 with the interlayer insulating film 17 and etching the interlayer insulating film 17 is performed. When the first semiconductor layer 15 and the second semiconductor layer 16 are not formed on the upper surface of the second insulating film 13, etching residue or damage occurs in the surface of the second insulating film 13 due to the step of etching the interlayer insulating film 17. As a result, a variation in the thickness of the second insulating film 13 occurs and a variation in the capacitive component region occurs.

(60) Therefore, when the first semiconductor layer 15 and the second semiconductor layer 16 are formed on the upper surface of the second insulating film 13, it is possible to form the capacitor C4 and the capacitor C5 having a stable capacitive component region, without being affected by the etching of the interlayer insulating film 17.

(61) The thickness of the second insulating film 13 can be changed to adjust the capacitance of the capacitor C2, the capacitor C4, and the capacitor C5, each having the second insulating film 13 as the capacitive component region, to necessary static electricity resistance.

(62) For example, when the temperature detecting diode 1 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, the thickness of the second insulating film 13 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(63) The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32. The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 , in order to use the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10 as the capacitive component region. When the first insulating film 12 is not used as the capacitive component region, the upper limit of the thickness of the first insulating film 12 is not particularly limited. For example, the thickness of the first insulating film 12 can be equal to the thickness of a field oxide film (not illustrated) which is formed on the first main surface (surface) of the semiconductor substrate 100.

(64) As described above, according to Embodiment 2, since the capacitive component region is formed between the conductive layer 14 and the temperature detecting diode 1, it is possible to improve the static electricity resistance of the temperature detecting diode 1, without increasing the area of the temperature detecting diode 1. In addition, according to Embodiment 2, since the capacitive component region is formed between the conductive layer 14 and the first semiconductor region 10 below the temperature detecting diode 1, it is possible to further improve the static electricity resistance of the temperature detecting diode 1.

(65) According to Embodiment 2, since the capacitive component region is formed between the conductive layer 14 and the first and second semiconductor layers 15 and 16 below the anode metal wiring line 6 and the cathode metal wiring line 7, it is possible to improve the static electricity resistance of the temperature detecting diode 1, without reducing the area of the active region 8. In addition, according to Embodiment 2, since the capacitive component region is formed between the conductive layer 14 and the first semiconductor region 10 below the anode metal wiring line 6 and the cathode metal wiring line 7, it is possible to further improve the static electricity resistance of the temperature detecting diode 1.

(66) Embodiment 3

(67) The protective diode 21 according to Embodiment 1 will be described in detail as a semiconductor device according to Embodiment 3 of the invention. FIG. 5 is a diagram illustrating the structure of the semiconductor device according to Embodiment 3 of the invention. The planar structure of the semiconductor device according to Embodiment 3 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 5(A) is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line C-C of FIG. 1(A) and FIG. 5(B) is an equivalent circuit diagram of FIG. 5(A).

(68) As illustrated in FIG. 5, in the semiconductor device according to Embodiment 3, the n.sup. first semiconductor layer 9, which will be the drift region of the MOSFET 51, is formed on the first main surface side of the semiconductor substrate 100. The p-type first semiconductor region 10, which will be the base region of the MOSFET 51, is formed in a surface layer of the first semiconductor layer 9. The n.sup.+ drain region 38 is formed on the second main surface side of the semiconductor substrate 100. The drain electrode 37 is formed on the surface of the drain region 38.

(69) The trench 31 is formed in the active region 8 so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. The gate insulating film 32 is formed in the trench 31 along the inner wall of the trench 31. In addition, the gate electrode 33 is provided in the trench 31, with the gate insulating film 32 interposed therebetween. The gate insulating film 32 is an oxide film. The gate electrode 33 is covered with the interlayer insulating film 17 which is made of polysilicon doped with impurities. The n.sup.+ second semiconductor region 11, which will be a source region, is formed adjacent to the side wall of the trench 31. The source electrode 34 comes into contact with the second semiconductor region 11 and the first semiconductor region 10.

(70) The protective diode 21 is arranged between the source electrode 34 and the gate electrode pad 5. The first insulating film 12 is formed on the first semiconductor region 10 below the protective diode 21. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage. The n.sup.+ conductive layer 14 which is made of polysilicon doped with impurities is formed on the upper surface of the first insulating film 12. The second insulating film 13 is formed on the upper surface of the conductive layer 14. The protective diode 21 which is made of polysilicon is formed on the upper surface of the second insulating film 13. The protective diode 21 is connected between the gate G (gate electrode pad 5) and the source S (source electrode 34). The second insulating film 13 is an oxide film. The thickness of the second insulating film 13 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage.

(71) The protective diode 21 provided between the gate G and the source S is a multi-stage bidirectional zener diode including the p.sup.+ layer 111 and the n.sup.+ layer 112. That is, in the protective diode 21, the p.sup.+ layer 111 and the n.sup.+ layer 112 are alternately arranged in the direction in which the p.sup.+ layer 111 and the n.sup.+ layer 112 are arranged in a line. The n.sup.+ layers 112 are provided at both ends of the protective diode 21. The n.sup.+ layer 112 provided at one end is connected to the gate G and the n.sup.+ layer 112 provided at the other end is connected to the source S. The p.sup.+ layer 111 is made of polysilicon doped with, for example, boron. The n.sup.+ layer 112 is made of polysilicon doped with, for example, arsenic or phosphorus.

(72) The conductive layer 14 is made of, for example, polysilicon doped with n-type impurities at an impurity concentration of 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3. For example, the conductive layer 14 is formed at the same time as the gate electrode 33 provided in the trench 31. Therefore, the conductive layer 14 may have a thickness required to fill the trench 31. In this embodiment, the thickness of the conductive layer 14 may be, for example, about 0.5 m.

(73) The conductive layer 14 is electrically insulated from the gate electrode 33, the source electrode 34, the drain electrode 35, the anode electrode, and the cathode electrode by the interlayer insulating film 17 and the second insulating film 13. Therefore, it is possible to prevent the adverse effect of a surge voltage applied to each electrode on the conductive layer 14.

(74) As such, the first insulating film 12, the conductive layer 14, and the second insulating film 13 are formed on the first semiconductor region 10 and the protective diode 21 is provided on the upper surface of the second insulating film 13. Therefore, it is possible to form a capacitor C7 (C7a to C7e) which has the second insulating film 13 provided between the protective diode 21 and the conductive layer 14 as a capacitive component region. In addition, it is possible to form a capacitor C6 which has the first insulating film 12 provided between the conductive layer 14 and the first semiconductor region 10 as a capacitive component region.

(75) The thickness of the second insulating film 13 can be changed to adjust the capacitance of the capacitor C7, which has the second insulating film 13 as the capacitive component region, to necessary static electricity resistance. For example, when the protective diode 21 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, the thickness of the second insulating film 13 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(76) The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32. The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 , in order to use the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10 as the capacitive component region. When the first insulating film 12 is not used as the capacitive component region, the upper limit of the thickness of the first insulating film 12 is not particularly limited. For example, the thickness of the first insulating film 12 can be equal to the thickness of a field oxide film (not illustrated) which is formed on the first main surface of the semiconductor substrate 100.

(77) As described above, according to Embodiment 3, since the capacitive component region is formed between the conductive layer 14 and the protective diode 21, it is possible to improve the static electricity resistance of the protective diode 21, without increasing the area of the protective diode 21. In addition, according to Embodiment 3, since the capacitive component region is formed between the conductive layer 14 and the first semiconductor region 10 below the protective diode 21, it is possible to further improve the static electricity resistance of the protective diode 21.

(78) Embodiment 4

(79) The protective diode 22 according to Embodiment 1 will be described in detail as a semiconductor device according to Embodiment 4 of the invention. FIG. 6 is a diagram illustrating the structure of the semiconductor device according to Embodiment 4 of the invention. The planar structure of the semiconductor device according to Embodiment 4 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 6(A) is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line D-D of FIG. 1(A) and FIG. 6(B) is an equivalent circuit diagram of FIG. 6(A).

(80) As illustrated in FIG. 6, in the semiconductor device according to Embodiment 4, the n.sup. first semiconductor layer 9, which will be the drift region of the MOSFET 51, is formed on the first main surface side of the semiconductor substrate 100. The p-type first semiconductor region 10, which will be the base region of the MOSFET 51, is formed in a surface layer of the first semiconductor layer 9 close to the gate electrode pad 5 (the inside). An n.sup.+ drain region 36 is formed in a surface layer of the first semiconductor layer 9 close to a drain electrode 35 (outer circumferential side). The n.sup.+ drain region 38 is formed on the second main surface side of the semiconductor substrate 100. The drain electrode 37 is formed on the surface of the drain region 38.

(81) The protective diode 22 is arranged between the gate electrode pad 5 and the drain electrode 35. The first insulating film 12 is formed on the first main surface of the semiconductor substrate 100 so as to extend over the first semiconductor region 10 close to the gate electrode pad 5 and the drain region 36 close to the drain electrode 35. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage. The n.sup.+ conductive layer 14 which is made of polysilicon doped with impurities is formed on the upper surface of the first insulating film 12. The second insulating film 13 is formed on the upper surface of the conductive layer 14. The protective diode 22 which is made of polysilicon is formed on the upper surface of the second insulating film 13. The protective diode 22 is connected between the gate G (gate electrode pad 5) and the drain D (drain electrode 35). The second insulating film 13 is an oxide film. The thickness of the second insulating film 13 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, electrostatic or overvoltage.

(82) The protective diode 22 provided between the gate G and the drain D is a multi-stage bidirectional zener diode including the p.sup.+ layer 111 and the n.sup.+ layer 112. That is, in the protective diode 22, the p.sup.+ layer 111 and the n.sup.+ layer 112 are alternately arranged in the direction in which the p.sup.+ layer 111 and the n.sup.+ layer 112 are arranged in a line. The n.sup.+ layers 112 are provided at both ends of the protective diode 22. The n.sup.+ layer 112 provided at one end is connected to the gate G and the n.sup.+ layer 112 provided at the other end is connected to the drain D. The p.sup.+ layer 111 is made of polysilicon doped with, for example, boron. The n.sup.+ layer 112 is made of polysilicon doped with, for example, arsenic or phosphorus.

(83) The conductive layer 14 is made of, for example, polysilicon doped with n-type impurities at an impurity concentration of 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3. For example, the conductive layer 14 is formed at the same time as the gate electrode 33 provided in the trench 31. Therefore, the conductive layer 14 may have a thickness required to fill the trench 31. In this embodiment, the thickness of the conductive layer 14 may be, for example, about 0.5 m.

(84) The conductive layer 14 is electrically insulated from the gate electrode 33, the source electrode 34, the drain electrode 35, the anode electrode, and the cathode electrode by the interlayer insulating film 17 and the second insulating film 13. Therefore, it is possible to prevent the adverse effect of a surge voltage applied to each electrode on the conductive layer 14.

(85) As such, the first insulating film 12, the conductive layer 14, and the second insulating film 13 are formed on the first semiconductor region 10 and the protective diode 22 is provided on the upper surface of the second insulating film 13. Therefore, it is possible to form a capacitor C9 (C9a to C9e) which has the second insulating film 13 provided between the protective diode 22 and the conductive layer 14 as a capacitive component region. In addition, it is possible to form a capacitor C8 which has the first insulating film 12 provided between the conductive layer 14 and the semiconductor substrate 100 as a capacitive component region.

(86) The thickness of the second insulating film 13 can be changed to adjust the capacitance of the capacitor C9, which has the second insulating film 13 as the capacitive component region, to necessary static electricity resistance. For example, when the protective diode 22 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, the thickness of the second insulating film 13 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(87) The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32. The thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 , in order to use the first insulating film 12 between the conductive layer 14 and the semiconductor substrate 100 as the capacitive component region. When the first insulating film 12 is not used as the capacitive component region, the upper limit of the thickness of the first insulating film 12 is not particularly limited. For example, the thickness of the first insulating film 12 can be equal to the thickness of a field oxide film (not illustrated) which is formed on the first main surface of the semiconductor substrate 100.

(88) As described above, according to Embodiment 4, the same effect as that in Embodiments 1 to 3 is obtained. In addition, according to Embodiment 4, since the capacitive component region is formed between the conductive layer 14 and the protective diode 22, it is possible to improve the static electricity resistance of the protective diode 22, without increasing the area of the protective diode 22. Furthermore, according to Embodiment 4, since the capacitive component region is formed between the first semiconductor region 10 and the conductive layer 14 below the protective diode 22, it is possible to further improve the static electricity resistance of the protective diode 22.

(89) Embodiment 5

(90) A semiconductor device according to Embodiment 5 will be described. FIG. 7 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 5 of the invention. FIG. 8 is a cross-sectional view illustrating another example of the structure of the semiconductor device according to Embodiment 5 of the invention. The semiconductor device according to Embodiment 5 is a modification of the semiconductor device according to Embodiment 2. The planar structure of the semiconductor device according to Embodiment 5 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. The semiconductor device according to Embodiment 5 differs from the semiconductor device according to Embodiment 2 in that a portion of an interlayer insulating film 17 interposed between a first semiconductor layer 15 and a second semiconductor layer 16 is a capacitive component region.

(91) FIG. 7 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 5 taken along the cutting line B-B of FIG. 1. The gap between the first semiconductor layer 15 below an anode metal wiring line 6 and the second semiconductor layer 16 below a cathode metal wiring line 7 is narrowed to form a capacitor C10 which has the interlayer insulating film 17 provided between the first semiconductor layer 15 and the second semiconductor layer 16 as the capacitive component region. The gap between the first semiconductor layer 15 and the second semiconductor layer 16 may be, for example, about 0.5 m.

(92) FIG. 8 is a cross-sectional view illustrating another example of the cross-sectional structure of the semiconductor device according to Embodiment 5 taken along the cutting line B-B of FIG. 1. The interlayer insulating film 17 is formed such that a concave portion is provided between the first semiconductor layer 15 and the second semiconductor layer 16. Then, the anode metal wiring line 6 is formed so as to fill the concave portion of the interlayer insulating film 17. In this way, it is possible to form a capacitor C11 which has the interlayer insulating film 17 between the anode metal wiring line 6 and the second semiconductor layer 16 as a capacitive component region.

(93) In the semiconductor devices illustrated in FIGS. 7 and 8, it is possible to form the capacitive component region below the anode metal wiring line 6 and the cathode metal wiring line 7 which are provided from the temperature detecting diode 1 to the anode electrode pad 3 and the cathode electrode pad 4, without reducing the area of the active region 8, and to improve the static electricity resistance of the temperature detecting diode 1.

(94) As described above, according to Embodiment 5, the same effect as that in Embodiments 1 to 4 is obtained.

(95) Embodiment 6

(96) A semiconductor device according to Embodiment 6 will be described. FIGS. 9 and 10 are cross-sectional views illustrating the structure of the semiconductor device according to Embodiment 6 of the invention. The semiconductor device according to Embodiment 6 is a modification of the semiconductor device according to Embodiment 2. The planar structure of the semiconductor device according to Embodiment 6 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. The semiconductor device according to Embodiment 6 differs from the semiconductor device according to Embodiment 2 in that a conductive layer 14 is divided into a plurality of parts by a second insulating film 13 which passes through the conductive layer 14 in the thickness direction.

(97) FIG. 9 is a cross-sectional view illustrating the cross-sectional structure of a temperature detecting diode 1 taken along the cutting line A-A of FIG. 1 in the semiconductor device according to Embodiment 6. The conductive layer 14 is divided into a conductive layer 14a and a conductive layer 14b for each conductivity-type layer (a p.sup.+ layer 111 and an n.sup.+ layer 112) of the temperature detecting diode 1 which is formed on the conductive layer 14 with the second insulating film 13 interposed therebetween. Specifically, the conductive layer 14 is divided into the conductive layer 14a which faces the p.sup.+ layer 111, with the second insulating film 13 interposed therebetween, and the conductive layer 14b which faces the n.sup.+ layer 112, with the second insulating film 13 interposed therebetween. A space between the divided conductive layers 14a and 14b is filled with the second insulating film 13. Therefore, it is possible to form a capacitor C12 which has the second insulating film 13 between the conductive layer 14a and the conductive layer 14b as a capacitive component region.

(98) FIG. 10 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 6 taken along the cutting line B-B of FIG. 1. The conductive layer 14 is divided into a conductive layer 14a close to the first semiconductor layer 15 that is formed on the conductive layer 14, with the second insulating film 13 interposed therebetween, and a conductive layer 14b close to the second semiconductor layer 16 that is formed on the conductive layer 14, with the second insulating film 13 interposed therebetween. That is, the conductive layer 14 is divided into the conductive layer 14a which faces the first semiconductor layer 15, with the second insulating film 13 interposed therebetween, and the conductive layer 14b which faces the second semiconductor layer 16, with the second insulating film 13 interposed therebetween. A space between the divided conductive layers 14a and 14b is filled with the second insulating film 13.

(99) It is possible to form a capacitor C13 which has the second insulating film 13 between the conductive layer 14a and the conductive layer 14b as a capacitive component region. Reference numerals C3a and C3b denote capacitors which have the first insulating film 12 between the conductive layers 14a and 14b and the first semiconductor region 10 as a capacitive component region. As illustrated in FIGS. 9 and 10, the conductive layer 14 may be provided in portions which face each conductivity-type layer forming the element that is arranged on the upper surface of the conductive layer 14, with the second insulating film 13 interposed therebetween. For example, this structure can also be applied to the protective diode 21 between the gate G and the source S described in Embodiment 3 or the protective diode 22 between the gate G and the drain D described in Embodiment 4.

(100) As described above, according to Embodiment 6, the same effect as that in Embodiments 1 to 5 is obtained.

(101) Embodiment 7

(102) A semiconductor device according to Embodiment 7 of the invention will be described. FIG. 11 is a diagram illustrating the structure of the semiconductor device according to Embodiment 7 of the invention. The semiconductor device according to Embodiment 7 is a modification of Embodiment 3. The planar structure of the semiconductor device according to Embodiment 7 is the same as the semiconductor device according to Embodiment 1 illustrated in FIG. 1. The semiconductor device according to Embodiment 7 differs from the semiconductor device according to Embodiment 3 in that a conductive layer 14 is divided into a conductive layer 14a, on which the protective diode 21 is arranged, and a conductive layer 14b, on which the protective diode 21 is not arranged, by a second insulating film 13 which passes through the conductive layer 14 in the thickness direction.

(103) FIG. 11(A) is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 7 taken along the cutting line C-C of FIG. 1. FIG. 11(B) is an equivalent circuit diagram of FIG. 11(A). The conductive layer 14 is divided into the conductive layers 14a and 14b, as illustrated in FIG. 11. The second insulating film 13, which is an oxide film with a thickness that is equal to or greater than the thickness of a gate insulating film 32, is formed on the upper surface of the divided conductive layer 14a. The protective diode 21 is formed on the upper surface of the second insulating film 13. The conductive layer 14b is connected to a source electrode 34.

(104) In this case, the conductive layer 14a is electrically insulated from a gate electrode 33, the source electrode 34, a drain electrode 35, an anode electrode, and a cathode electrode by an interlayer insulating film 17 and the second insulating film 13. It is possible to form a capacitor C14 which has the interlayer insulating film 17 between the conductive layer 14a and the conductive layer 14b as a capacitive component region.

(105) As described above, according to Embodiment 7, the same effect as that in Embodiments 1 to 6 is obtained.

(106) Embodiment 8

(107) A semiconductor device according to Embodiment 8 of the invention will be described. FIGS. 12 and 14 are cross-sectional views illustrating the structure of the semiconductor device according to Embodiment 8 of the invention. FIG. 13 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 8 of the invention. The planar structure of the semiconductor device according to Embodiment 8 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 12 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 8 taken along the cutting line A-A of FIG. 1. FIG. 13 is an equivalent circuit diagram of FIG. 12. FIG. 14 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 8 taken along the cutting line B-B of FIG. 1. The semiconductor device according to Embodiment 8 of the invention differs from the semiconductor device according to Embodiment 2 of the invention in that a conductive layer 14 and a second insulating film 13 are not provided and a temperature detecting diode 1, an anode metal wiring line 6, and a cathode metal wiring line 7 are formed on the upper surface of a first insulating film 12.

(108) As illustrated in FIGS. 12 to 14, in the semiconductor device according to Embodiment 8, an n first semiconductor layer 9, which will be a drift region of a MOSFET 51, is formed on the first main surface side of a semiconductor substrate 100. A p-type first semiconductor region 10, which will be a base region of the MOSFET 51, is formed in a surface layer of the first semiconductor layer 9. An n.sup.+ drain region 38 is formed on the second main surface side of the semiconductor substrate 100. A drain electrode 37 is formed on the surface of the drain region 38.

(109) A trench 31 is formed in an active region 8 so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. A gate insulating film 32 is formed in the trench 31 along the inner wall of the trench 31. A gate electrode 33 is provided in the trench 31, with the gate insulating film 32 interposed therebetween. The gate insulating film 32 is an oxide film. The gate electrode 33 is covered with an interlayer insulating film 17 which is made of polysilicon doped with impurities. An n.sup.+ second semiconductor region 11, which will be a source region, is formed adjacent to the side wall of the trench 31. A source electrode 34 comes into contact with the second semiconductor region 11 and the first semiconductor region 10.

(110) The first insulating film 12 is formed on the first semiconductor region 10 below the temperature detecting diode 1. The temperature detecting diode 1 which is made of polysilicon is formed on the upper surface of the first insulating film 12. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage.

(111) The temperature detecting diode 1 is formed by connecting a plurality of zener diodes, each having a p.sup.+ layer 111 and an n.sup.+ layer 112, in series to each other. The p.sup.+ layer 111 is made of polysilicon doped with, for example, boron. The n.sup.+ layer 112 is made of polysilicon doped with, for example, arsenic or phosphorus.

(112) Below the anode metal wiring line 6 which connects the temperature detecting diode 1 and an anode electrode pad 3, the first insulating film 12, which is an oxide film with a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the first semiconductor region 10. A first semiconductor layer 15 is formed on the upper surface of the first insulating film 12.

(113) Below the cathode metal wiring line 7 which connects the temperature detecting diode 1 and a cathode electrode pad 4, the first insulating film 12, which is an oxide film with a thickness that is equal to or greater than the thickness of the gate insulating film 32, is formed on the first semiconductor region 10. A second semiconductor layer 16 is formed on the upper surface of the first insulating film 12.

(114) The first semiconductor layer 15 and the second semiconductor layer 16 are made of polysilicon doped with impurities. The thickness of the first semiconductor layer 15 and the second semiconductor layer 16 is in the range of, for example, about 0.5 m to 1 m. The formation of polysilicon, ion implantation, and thermal diffusion for forming the first semiconductor layer 15 and the second semiconductor layer 16 are performed in the same step as the formation of the temperature detecting diode 1. The conductivity type of the first semiconductor layer 15 and the second semiconductor layer 16 may be a p type or an n type. When polysilicon is, for example, a p type, boron can be used as the impurities added to polysilicon. When polysilicon is an n type, arsenic or phosphorus can be used as the impurities.

(115) The first semiconductor layer 15 below the anode metal wiring line 6 and the second semiconductor layer 16 below the cathode metal wiring line 7 are formed on the same first semiconductor region 10 and the same first insulating film 12. In addition, the temperature detecting diode 1, the first semiconductor layer 15 below the anode metal wiring line 6, and the second semiconductor layer 16 below the cathode metal wiring line 7 are formed on the same first semiconductor region 10 and the same first insulating film 12.

(116) As such, since the first insulating film 12 is formed on the first semiconductor region 10 and the temperature detecting diode 1 is provided on the upper surface of the first insulating film 12, it is possible to form a capacitor C41 (C41a to C41j), which has the first insulating film 12 between the first semiconductor region 10 and the temperature detecting diode 1 as a capacitive component region, below the temperature detecting diode 1.

(117) Since the first insulating film 12 is formed on the first semiconductor region 10 and the first semiconductor layer 15 is provided on the upper layer of the first insulating film 12, it is possible to form a capacitor C42, which has the first insulating film 12 between the first semiconductor region 10 and the first semiconductor layer 15 as a capacitive component region, below the anode metal wiring line 6.

(118) Since the first insulating film 12 is formed on the first semiconductor region 10 and the second semiconductor layer 16 is provided on the upper layer of the first insulating film 12, it is possible to form a capacitor C43, which has the first insulating film 12 between the first semiconductor region 10 and the second semiconductor layer 16 as a capacitive component region, below the cathode metal wiring line 7.

(119) In order to use the first insulating film 12 as the capacitive component region, the anode metal wiring line 6 and the cathode metal wiring line 7 can be directly formed on the first insulating film 12, without forming the first semiconductor layer 15 and the second semiconductor layer 16. However, this structure is not preferable for the following reason. Before the anode metal wiring line 6 and the cathode metal wiring line 7 are formed, a step of covering the first main surface of the semiconductor substrate 100 with the interlayer insulating film 17 and etching the interlayer insulating film 17 is performed. When the first semiconductor layer 15 and the second semiconductor layer 16 are not formed on the upper surface of the first insulating film 12, etching residue or damage occurs in the surface of the first insulating film 12 due to the step of etching the interlayer insulating film 17. As a result, a variation in the thickness of the first insulating film 12 occurs and a variation in the capacitive component region occurs.

(120) Therefore, when the first semiconductor layer 15 and the second semiconductor layer 16 are formed on the upper surface of the first insulating film 12, it is possible to form the capacitor C42 and the capacitor C43 having the stable capacitive component region, without being affected by the etching of the interlayer insulating film 17.

(121) The thickness of the first insulating film 12 can be changed to adjust the capacitance of the capacitor C41, the capacitor C42, and the capacitor C43, each having the first insulating film 12 as the capacitive component region, to necessary static electricity resistance.

(122) For example, when the temperature detecting diode 1 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, the thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(123) As described above, according to Embodiment 8, since the capacitive component region is formed between the temperature detecting diode 1 and the first semiconductor region 10 below the temperature detecting diode 1, it is possible to improve the static electricity resistance of the temperature detecting diode 1, without increasing the area of the temperature detecting diode 1.

(124) According to Embodiment 8, since the capacitive component region is formed between the first semiconductor region 10 below the anode metal wiring line 6 and the cathode metal wiring line 7 and the first and second semiconductor layers 15 and 16, it is possible to improve the static electricity resistance of the temperature detecting diode 1, without reducing the area of the active region 8.

(125) Embodiment 9

(126) A semiconductor device according to Embodiment 9 will be described. FIG. 15 is a diagram illustrating the structure of the semiconductor device according to Embodiment 9 of the invention. The planar structure of the semiconductor device according to Embodiment 9 is the same as the planar structure in the Embodiment 1 illustrated in FIG. 1. FIG. 15(A) is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 9 taken along the cutting line C-C of FIG. 1. FIG. 15(B) is an equivalent circuit diagram of FIG. 15(A). The semiconductor device according to Embodiment 9 of the invention differs from the semiconductor device according to Embodiment 3 in that a conductive layer 14 and a second insulating film 13 are not provided and a protective diode 21 is formed on the upper surface of a first insulating film 12.

(127) As illustrated in FIG. 15, in the semiconductor device according to Embodiment 9, an n.sup. first semiconductor layer 9, which will be a drift region of a MOSFET 51, is formed on the first main surface side of a semiconductor substrate 100. A p-type first semiconductor region 10, which will be a base region of the MOSFET 51, is formed in a surface layer of the first semiconductor layer 9. An n.sup.+ drain region 38 is formed on the second main surface side of the semiconductor substrate 100. A drain electrode 37 is formed on the surface of the drain region 38.

(128) A trench 31 is formed in an active region 8 so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. A gate insulating film 32 is formed in the trench 31 along the inner wall of the trench 31. A gate electrode 33 is provided in the trench 31, with the gate insulating film 32 interposed therebetween. The gate insulating film 32 is an oxide film. The gate electrode 33 is covered with an interlayer insulating film 17 which is made of polysilicon doped with impurities. An n.sup.+ second semiconductor region 11, which will be a source region, is formed adjacent to the side wall of the trench 31. A source electrode 34 comes into contact with the second semiconductor region 11 and the first semiconductor region 10.

(129) The protective diode 21 is arranged between the source electrode 34 and the gate electrode pad 5. Below the protective diode 21, the first insulating film 12 is formed on the first semiconductor region 10. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage. The protective diode 21 which is made of polysilicon is formed on the upper surface of the first insulating film 12. The protective diode 21 is connected to between a gate G and a source S.

(130) The protective diode 21 provided between the gate G and the source S is a multi-stage bidirectional zener diode including a p.sup.+ layer 111 and a n.sup.+ layer 112. The p.sup.+ layer 111 is made of polysilicon doped with, for example, boron. The n.sup.+ layer 112 is made of polysilicon doped with, for example, arsenic or phosphorus.

(131) As such, since the first insulating film 12 is formed on the first semiconductor region 10 and the protective diode 21 is provided on the upper surface of the first insulating film 12, it is possible to form a capacitor C44 (C44a to C44e), which has the first insulating film 12 between the first semiconductor region 10 and the protective diode 21 as a capacitive component region, below the protective diode 21 provided between the gate G and the source S.

(132) The thickness of the first insulating film 12 can be changed to adjust the capacitance of the capacitor C44 having the first insulating film 12 as the capacitive component region to necessary static electricity resistance. For example, when the protective diode 21 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, that the thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(133) As described above, according to Embodiment 9, since the capacitive component region is formed between the first semiconductor region 10 and the protective diode 21 below the protective diode 21 provided between the gate G and the source S, it is possible to improve the static electricity resistance of the protective diode 21, without increasing the area of the protective diode 21.

(134) Embodiment 10

(135) A semiconductor device according to Embodiment 10 of the invention will be described. FIG. 16 is a diagram illustrating the structure of the semiconductor device according to Embodiment 10 of the invention. The planar structure of the semiconductor device according to Embodiment 10 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 16(A) is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 10 taken along the cutting line D-D of FIG. 1. FIG. 16(B) is an equivalent circuit diagram of FIG. 16(A). The semiconductor device according to Embodiment 10 of the invention differs from the semiconductor device according to Embodiment 4 in that a conductive layer 14 and a second insulating film 13 are not provided and a protective diode 22 is formed on the upper surface of a first insulating film 12.

(136) As illustrated in FIG. 16, in the semiconductor device according to Embodiment 10, an n.sup. first semiconductor layer 9, which will be a drift region of a MOSFET 51, is formed on the first main surface side of a semiconductor substrate 100. A p-type first semiconductor region 10, which will be a base region of the MOSFET 51, is formed in the first semiconductor layer 9 close to the gate electrode pad 5. An n.sup.+ drain region 36 is formed in a surface layer of the first semiconductor layer 9 which is close to a drain electrode 35. A drain region 38 is formed on the second main surface side of the semiconductor substrate 100. A drain electrode 37 is formed on the surface of the drain region 38.

(137) The protective diode 22 is arranged between a gate electrode pad 5 and the drain electrode 35. The first insulating film 12 is formed on the first main surface of the semiconductor substrate 100 so as to extend over the first semiconductor region 10 close to the gate electrode pad 5 and the drain region 36 close to the drain electrode 35. A protective diode 22 which is made of polysilicon is formed on the upper surface of the first insulating film 12. The protective diode 22 is connected between a gate G and a drain D. The first insulating film 12 is an oxide film. The thickness of the first insulating film 12 is equal to or greater than the thickness of the gate insulating film 32 in terms of voltage breakdown due to, for example, static electricity or overvoltage.

(138) The protective diode 22 connected between the gate G and the drain D is a multi-stage bidirectional zener diode including a p.sup.+ layer 111 and an n.sup.+ layer 112. The p.sup.+ layer 111 is made of polysilicon doped with, for example, boron. The n.sup.+ layer 112 is made of polysilicon doped with, for example, arsenic or phosphorus.

(139) As such, the first insulating film 12 is formed on the first semiconductor region 10 and the protective diode 22 is provided on the upper surface of the first insulating film 12. Therefore, it is possible to form a capacitor C45 (C45a to C45e), which has the first insulating film 12 between the semiconductor substrate 100 and the protective diode 22 as a capacitive component region, below the protective diode 22 provided between the gate G and the drain D.

(140) The thickness of the first insulating film 12 can be changed to adjust the capacitance of the capacitor C45, which has the first insulating film 12 as the capacitive component region, to necessary static electricity resistance. For example, when the protective diode 22 has an electrostatic breakdown voltage of about 200 V, a capacitance of about 90 pF is required. Therefore, the thickness of the first insulating film 12 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 .

(141) As described above, according to Embodiment 10, the capacitive component region is formed between the semiconductor substrate 100, which is arranged below the protective diode 22 provided between the gate G and the drain D, and the protective diode 22. Therefore, it is possible to improve the static electricity resistance of the protective diode 22, without increasing the area of the protective diode 22.

(142) Embodiment 11

(143) A semiconductor device according to Embodiment 11 of the invention will be described. FIG. 17 is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 11 of the invention. The planar structure of the semiconductor device according to Embodiment 11 is the same as the planar structure in Embodiment 1 illustrated in FIG. 1. FIG. 17 illustrates the cross-sectional structure of the semiconductor device according to Embodiment 11 taken along the cutting line B-B of FIG. 1. The semiconductor device according to Embodiment 11 is a modification of the semiconductor device according to Embodiment 8. The semiconductor device according to Embodiment 11 differs from the semiconductor device according to Embodiment 8 in that a portion of an interlayer insulating film 17 interposed between a first semiconductor layer 15 and a second semiconductor layer 16 is a capacitive component region.

(144) As illustrated in FIG. 17, the gap between the first semiconductor layer 15 below an anode metal wiring line 6 and the second semiconductor layer 16 below a cathode metal wiring line 7 is narrowed to form a capacitor C46 which has the interlayer insulating film 17 provided between the first semiconductor layer 15 and the second semiconductor layer 16 as the capacitive component region. The gap between the first semiconductor layer 15 and the second semiconductor layer 16 may be, for example, about 0.5 m.

(145) As described above, according to Embodiment 11, it is possible to form a capacitive component region below the anode metal wiring line 6 and the cathode metal wiring line 7 which are provided from a temperature detecting diode 1 to an anode electrode pad 3 and a cathode electrode pad 4, without reducing the area of an active region 8. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode 1.

(146) Embodiment 12

(147) A method for producing a semiconductor device according to Embodiment 12 of the invention will be described. FIG. 18 is a cross-sectional view illustrating the method for producing the semiconductor device according to Embodiment 12 of the invention. A method for producing the protective diode 21 between the gate G and the source S according to Embodiment 3 will be described as an example of Embodiment 12.

(148) First, as illustrated in FIG. 18(A), the trench 31 is formed in the semiconductor substrate 100, in which the first semiconductor region 10 is formed in the surface layer of the first semiconductor layer 9 by diffusion, so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. Then, the first insulating film 12 is formed on the surface of the semiconductor substrate 100 (the first main surface of the semiconductor substrate 100 and the inner wall of the trench 31) by thermal oxidation. The first insulating film 12 which is formed along the inner wall of the trench 31 is the gate insulating film 32. That is, the first insulating film 12 is formed in the same step as the gate insulating film 32.

(149) Then, polysilicon for forming the conductive layer 14 is deposited on the first insulating film 12 by a chemical vapor deposition (CVD) method while being doped with n-type impurities. The impurity concentration of the conductive layer 14 is in the range of, for example, 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3. In this case, the conductive layer 14 provided in the trench 31 is the gate electrode 33. That is, the conductive layer 14 is formed in the same step as polysilicon for forming the gate electrode 33 is deposited.

(150) Then, as illustrated in FIG. 18(B), the conductive layer 14 is patterned and the gate electrode 33 is formed in the trench 31. In addition, the conductive layer 14 is formed on the first insulating film 12. In this case, the thickness of the conductive layer 14 is, for example, 0.5 m.

(151) Then, as illustrated in FIG. 18(C), the second insulating film 13 is formed with a thickness that is equal to or greater than the thickness of the gate insulating film 32 on the entire surface of the conductive layer 14 by thermal oxidation or the CVD method. The thickness of the second insulating film 13 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 . Then, a semiconductor layer 18 which is made of undoped polysilicon for forming the protective diode 21 is formed with a thickness of, for example, 0.5 m to 1 m on the second insulating film 13 by the CVD method and is then patterned.

(152) Then, as illustrated in FIG. 18(D), p-type impurity ions and n-type impurity ions are selectively implanted into the semiconductor layer 18 in this order and an activation process is performed to form the protective diode 21 including the p.sup.+ layer 111 and the n.sup.+ layer 112. The p-type impurity ions and the n-type impurity ions are sequentially implanted using a mask obtained by patterning a resist (not illustrated) formed on the semiconductor layer 18 in a predetermined pattern. At the same time as the n-type impurity ions are implanted, the n-type impurity ions are implanted into the first semiconductor region 10 in the active region 8 to form the second semiconductor region 11 in the surface layer of the first semiconductor region 10.

(153) In the implantation of the n-type ions, for example, arsenic is used as a dopant and impurity concentration is in the range of, for example, about 0.510.sup.20 cm.sup.3 to 2.510.sup.20 cm.sup.3. In the implantation of the p-type ions, for example, boron is used as the dopant and impurity concentration is in the range of, for example, about 0.510.sup.20 cm.sup.3 to 2.510.sup.20 cm.sup.3. The impurity concentration of the second semiconductor region 11 is in the range of, for example, about 0.510.sup.20 cm.sup.3 to 2.510.sup.20 cm.sup.3 and, for example, arsenic is used as the dopant.

(154) In addition, phosphorus may be used instead of arsenic which is implanted in the ion implantation. Then, as illustrated in FIG. 18(E), the interlayer insulating film 17 is formed on the first main surface of the semiconductor substrate 100 and is then patterned. In this case, the conductive layer 14 is electrically insulated from the gate electrode 33 or each electrode which is formed in the subsequent steps by the interlayer insulating film 17 and the second insulating film 13. Then, the other element structures are formed on the first main surface side of the semiconductor substrate 100 by a general method and a drain region or a drain electrode is formed on the second main surface side of the semiconductor substrate 100. In this way, the semiconductor device illustrated in FIG. 5 is completed.

(155) As an example of the method for producing the semiconductor device according to Embodiment 12, a method for producing the protective diode 21 has been described. However, the invention can also be applied to a method for producing the temperature detecting diode 1 and a method for producing the protective diode 22 between the gate G and the drain D.

(156) As described above, according to Embodiment 12, the first insulating film 12 is used as the gate insulating film 32 and polysilicon for forming the gate electrode 33 is used as the conductive layer 14. Therefore, it is possible to reduce the number of production steps.

(157) Embodiment 13

(158) FIG. 19 is a cross-sectional view illustrating a method for producing a semiconductor device according to Embodiment 13 of the invention. A method for producing a portion below the anode metal wiring line 6 and the cathode metal wiring line 7 which connect the temperature detecting diode 1 and the anode and cathode electrode pads 3 and 4 in Embodiment 2 will be described as an example of Embodiment 13.

(159) First, as illustrated in FIG. 19(A), the trench 31 is formed in the semiconductor substrate 100, in which the first semiconductor region 10 is formed in the surface layer of the first semiconductor layer 9 by diffusion, so as to extend from the first main surface of the semiconductor substrate 100 to the first semiconductor layer 9 through the first semiconductor region 10. Then, the first insulating film 12 is formed on the surface of the semiconductor substrate 100 (the first main surface of the semiconductor substrate 100 and the inner wall of the trench 31) by thermal oxidation. The first insulating film 12 which is formed along the inner wall of the trench 31 is the gate insulating film 32. That is, the first insulating film 12 is formed in the same step as the gate insulating film 32.

(160) Then, polysilicon for forming the conductive layer 14 is deposited on the first insulating film 12 by a CVD method while being doped with n-type impurities. The impurity concentration of the conductive layer 14 is in the range of, for example, 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3. In this case, the conductive layer 14 provided in the trench 31 is the gate electrode 33. That is, the conductive layer 14 is formed in the same step as polysilicon for forming the gate electrode 33 is deposited.

(161) Then, as illustrated in FIG. 19(B), the conductive layer 14 is patterned and the gate electrode 33 is formed in the trench 31. In addition, the conductive layer 14 is formed on the first insulating film 12. In this case, the thickness of the conductive layer 14 is in the range of, for example, 0.5 m to 1 m.

(162) Then, as illustrated in FIG. 19(C), the second insulating film 13 is formed with a thickness that is equal to or greater than the thickness of the gate insulating film 32 on the entire surface of the conductive layer 14 by thermal oxidation or the CVD method. The thickness of the second insulating film 13 may be equal to or greater than the thickness of the gate insulating film 32 and equal to or less than 1000 . Then, a semiconductor layer 18 which is made of undoped polysilicon for forming the first semiconductor layer 15 and the second semiconductor layer 16 is formed on the second insulating film 13 by the CVD method and is then patterned. The thickness of the first semiconductor layer 15 and the second semiconductor layer 16 is in the range of, for example, 0.5 m to 1 m.

(163) In addition, p-type impurity ions and n-type impurity ions are selectively implanted into the semiconductor layer in this order and an activation process is performed such that the first semiconductor layer 15 and the second semiconductor layer 16 have predetermined conductivity types. The p-type impurity ions and the n-type impurity ions for forming the first semiconductor layer 15 and the second semiconductor layer 16 are sequentially implanted using a mask obtained by patterning a resist (not illustrated) formed on the undoped semiconductor layer in a predetermined pattern. At the same time as the n-type impurity ions are implanted, the n-type impurity ions are implanted into the first semiconductor region 10 in the active region 8 to form the second semiconductor region 11 in the surface layer of the first semiconductor region 10.

(164) In the implantation of the n-type ions, for example, arsenic is used as a dopant and impurity concentration is in the range of, for example, about 0.510.sup.20 cm.sup.3 to 2.510.sup.20 cm.sup.3. In the implantation of the p-type ions, for example, boron is used as the dopant and impurity concentration is in the range of, for example, about 0.510.sup.20 cm.sup.3 to 2.5'10.sup.20 cm.sup.3.

(165) In addition, phosphorus may be used instead of arsenic which is implanted in the ion implantation. Then, as illustrated in FIG. 19(D), the interlayer insulating film 17 is formed on the first main surface of the semiconductor substrate 100 and is then patterned. In this case, the conductive layer 14 is electrically insulated from the gate electrode 33 or each electrode which is formed in the subsequent steps by the interlayer insulating film 17 and the second insulating film. Then, the other element structures are formed on the first main surface side of the semiconductor substrate 100 by a general method and a drain region or a drain electrode is formed on the second main surface side of the semiconductor substrate 100. In this way, the semiconductor device illustrated in FIG. 4 is completed.

(166) The first semiconductor layer 15 below the anode metal wiring line 6 and the second semiconductor layer 16 below the cathode metal wiring line 7 are formed at the same time as the temperature detecting diode 1. Therefore, the first insulating film 12, the conductive layer 14, and the second insulating film 13 below the anode metal wiring line 6 and the cathode metal wiring line 7 are each formed at the same time as the first insulating film 12, the conductive layer 14, and the second insulating film 13 in the step of forming the temperature detecting diode 1. The semiconductor layer which is made of undoped polysilicon for forming the first semiconductor layer 15 and the second semiconductor layer 16 is formed at the same time as the semiconductor layer which is made of undoped polysilicon for forming the temperature detecting diode 1.

(167) As described above, according to Embodiment 13, the first insulating film 12 is used as the gate insulating film 32 and polysilicon for forming the gate electrode 33 is used as the conductive layer 14. Therefore, it is possible to reduce the number of production steps.

(168) When the method for producing the semiconductor device according to Embodiment 13 is applied to Embodiments 8 to 11, the step of forming the conductive layer 14 and the second insulating film 13 may be omitted. In this case, a capacitive component region is formed between the temperature detecting diode 1 and the semiconductor substrate 100, between the protective diodes 21 and 22 and the semiconductor substrate 100, between the semiconductor substrate 100 and the first semiconductor layer 15 below the anode metal wiring line 6, or between the semiconductor substrate 100 and the second semiconductor layer 16 below the cathode metal wiring line 7.

(169) When the method for producing the semiconductor device according to Embodiment 13 is applied to Embodiments 1 to 7, a capacitive component region is formed between the temperature detecting diode 1 and the conductive layer 14, between the protective diodes 21 and 22 and the conductive layer 14, between the conductive layer 14 and the first semiconductor layer 15 below the anode metal wiring line 6, and between the conductive layer 14 and the second semiconductor layer 16 below the cathode metal wiring line 7. In addition, a capacitive component region can be formed between the conductive layer 14 and the semiconductor substrate 100. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode 1 and the protective diodes 21 and 22, as compared to Embodiments 8 to 11. I addition, since the conductive layer 14 is electrically insulated from the gate electrode 33, the source electrode 34, the drain electrode 35, the anode electrode, and the cathode electrode, it is possible to prevent the adverse effect of a surge voltage applied to each electrode.

(170) The invention is not limited to the above-described embodiments, but various modifications and changes of the invention can be made without departing from the scope and spirit of the invention. In addition, in each embodiment, the first conductivity type is an n type and the second conductivity type is a p type. However, the invention is not limited thereto. The first conductivity type may be a p type and the second conductivity type may be an n type. In this case, the same effect as described above is obtained.

(171) Embodiment 14

(172) A semiconductor device according to Embodiment 14 will be described.

(173) FIG. 22 is a diagram illustrating the structure of the semiconductor device according to Embodiment 14. FIG. 22 is a plan view illustrating the structure of the semiconductor device according to Embodiment 14.

(174) FIGS. 23, 25, 26, 27, and 28 are cross-sectional views illustrating the structure of the semiconductor device according to Embodiment 14. FIG. 24 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 14. FIG. 23 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line E-E of FIG. 22. FIG. 24 is an equivalent circuit diagram of FIG. 23. FIG. 25 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line F-F of FIG. 22. FIG. 26 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line G-G of FIG. 22. FIG. 27 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line H-H of FIG. 22. FIG. 28 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line I-I of FIG. 22.

(175) The cutting lines of FIG. 22 are different in position from those of the plan view illustrated in FIG. 1A. Also, the equivalent circuit diagrams of the protective diodes 21 and 22 are the same as in FIG. 1B.

(176) Embodiment 14 differs from Embodiment 2 in that the temperature detecting diode 1 is surrounded by a first conductive layer 24, which is electrically connected to the gate electrode 33, and a second conductive layer 25, as illustrated in FIGS. 25, 26, 27, and 28. In the temperature detecting diode 1, diodes, in each of which the p.sup.+ layer 111 and the n.sup.+ layer 112 are pn joined, are arranged in series in a longitudinal direction of the trench 31 and electrically connected to each other. At either end of the temperature detecting diode 1 parallel to the longitudinal direction of the trench 31, the second conductive layer 25 is disposed between the conductive layer 14, which is arranged below the p.sup.+ layer 111 and the n.sup.+ layer 112, and the active region 8, as illustrated in FIGS. 27 and 28. As illustrated in FIG. 26, the first conductive layer 24 is arranged at one end of the temperature detecting diode 1 in a direction perpendicular to the longitudinal direction of the trench 31. Also, as illustrated in FIG. 23, the second conductive layer 25 electrically connected to the gate electrode 33 is arranged at the other end of the temperature detecting diode 1 in the direction perpendicular to the longitudinal direction of the trench 31. As illustrated in FIGS. 23, 25, 26, 27 and 28, the first conductive layer 24 and the second conductive layer 25 are electrically connected. Therefore, the gate resistance around the temperature detecting diode 1 decreases.

(177) The first conductive layer 24 and the second conductive layer 25 are made of, for example, polysilicon doped with n type impurities at an impurity concentration of 410.sup.20 cm.sup.3 to 510.sup.20 cm.sup.3, in the same way as the conductive layer 14 of Embodiment 2. For example, the first conductive layer 24 and the second conductive layer 25 are formed at the same time as the gate electrode 33 provided in the trench 31, in the same way as the conductive layer 14 of Embodiment 2. The thickness of the first conductive layer 24 and the second conductive layer 25 may be, for example, about 0.5 m, in the same way as that of the conductive layer 14 of Embodiment 2.

(178) The first conductive layer 24 is formed on the first insulating film 12 formed on the upper surface of the first semiconductor region 10. The second conductive layer 25 is formed on the gate insulating film 32 formed on the upper surface of the first semiconductor region 10. The first insulating film 12 and the gate insulating film 32 may have the same thickness, and may be the same insulating film formed at the same time.

(179) As illustrated in FIG. 23, the first conductive layer 24 arranged below the second semiconductor layer 16 and the gate electrode 33 are electrically connected. Therefore, the gate resistance around the temperature detecting diode 1 decreases.

(180) Also, as illustrated in FIGS. 23, 26 and 27, in Embodiment 14, the upper portion of the first semiconductor layer 15 and the anode metal wiring line 6 are not electrically connected. In the same way, the upper portion of the second semiconductor layer 16 and the cathode metal wiring line 7 are not electrically connected either. Since the interlayer insulating film 17 is formed on the first semiconductor layer 15, and the anode metal wiring line 6 is arranged on the interlayer insulating film 17, the first semiconductor layer 15 and the anode metal wiring line 6 are insulated by an insulating film thicker than the second insulating film 13. In the same way, since the interlayer insulating film 17 is formed on the second semiconductor layer 16, and the cathode metal wiring line 7 is arranged on the interlayer insulating film 17, the second semiconductor layer 16 and the cathode metal wiring line 7 are insulated by an insulating film thicker than the second insulating film 13. As a result, the potential generated in the temperature detecting diode 1 and the potential applied to the gate electrode 33 are prevented from interacting each other.

(181) The capacitance of the capacitors C4 and C5 illustrated in FIG. 24 decreases, as compared to in Embodiment 2, but the static electricity resistance can be kept by the capacitors C1a to C1e formed in the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10, the capacitors C2a to C2j formed in the second insulating film 13 between the p.sup.+ layer 111 and the n.sup.+ layer 112, and the conductive layer 14, and the capacitor C3 formed in the first insulating film 12 between the first conductive layer 24 and the first semiconductor region 10.

(182) Embodiment 15

(183) A semiconductor device according to Embodiment 15 will be described. FIGS. 29, 31, and 32 are cross-sectional views illustrating the structure of the semiconductor device according to Embodiment 15. FIG. 30 is a circuit diagram illustrating the circuit structure of the semiconductor device according to Embodiment 15. The planar structure of the semiconductor device according to Embodiment 15 is the same as in Embodiment 14 shown in FIG. 22. FIG. 29 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line E-E of FIG. 22. FIG. 31 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line G-G of FIG. 22. FIG. 32 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line H-H of FIG. 22. FIG. 30 is an equivalent circuit diagram of FIG. 29. The cross-sectional structures taken along the cutting line F-F and cutting line I-I of FIG. 22 are the same as in Embodiment 14.

(184) Embodiment 15 differs from Embodiment 14 in that the first semiconductor layer 15 and the second semiconductor layer 16 are not formed above the first conductive layer 24 electrically connected to the gate electrode 33, as illustrated in FIGS. 29, 31, and 32.

(185) The capacitor C4 having the second insulating film and the interlayer insulating film 17 as the capacitive component region is provided between the first conductive layer 24 and the anode metal wiring line 6. The capacitor C5 having the second insulating film and the interlayer insulating film 17 as the capacitive component region is provided between the first conductive layer 24 and the cathode metal wiring line 7. As the capacitors C4 and C5 are small in capacitance, the capacitors C4 and C5 may be ignored, as in the equivalent circuit illustrated in FIG. 30. The static electricity resistance can be kept by the capacitors C1a to C1e, illustrated in FIG. 29, which are formed in the first insulating film 12 between the conductive layer 14 and the first semiconductor region 10, the capacitors C2a to C2j formed in the second insulating film 13 between the p.sup.+ layer 111 and the n.sup.+ layer 112, and the conductive layer 14, and the capacitor C3 formed in the first insulating film 12 between the first conductive layer 24 and the first semiconductor region 10.

(186) In Embodiment 15, the temperature detecting diode 1 is surrounded by the first conductive layer 24, which is electrically connected to the gate electrode 33, and the second conductive layer 25. Therefore, the gate resistance around the temperature detecting diode 1 decreases. Also, the first conductive layer 24 and the gate electrode 33 are electrically connected. Therefore, the gate resistance around the temperature detecting diode 1 decreases.

INDUSTRIAL APPLICABILITY

(187) As described above, the semiconductor devices and the semiconductor devices production methods according to the invention are useful for MOS semiconductor elements including a temperature detecting diode or a protective diode.

EXPLANATIONS OF LETTERS OR NUMERALS

(188) 1 TEMPERATURE DETECTING DIODE

(189) 2 PROTECTIVE DIODE

(190) 3 ANODE ELECTRODE PAD

(191) 4 CATHODE ELECTRODE PAD

(192) 5 GATE ELECTRODE PAD

(193) 6 ANODE METAL WIRING LINE

(194) 7 CATHODE METAL WIRING LINE

(195) 8 ACTIVE REGION

(196) 9 FIRST SEMICONDUCTOR LAYER

(197) 10 FIRST SEMICONDUCTOR REGION

(198) 11 SECOND SEMICONDUCTOR REGION (SOURCE REGION)

(199) 12 FIRST INSULATING FILM

(200) 13 SECOND INSULATING FILM

(201) 14, 14a, 14b CONDUCTIVE LAYER

(202) 15 FIRST SEMICONDUCTOR LAYER

(203) 16 SECOND SEMICONDUCTOR LAYER

(204) 17 INTERLAYER INSULATING FILM

(205) 18 SEMICONDUCTOR LAYER

(206) 19 INSULATING FILM

(207) 21 PROTECTIVE DIODE BETWEEN GATE AND SOURCE

(208) 22 PROTECTIVE DIODE BETWEEN GATE AND DRAIN

(209) 24 FIRST CONDUCTIVE LAYER

(210) 25 SECOND CONDUCTIVE LAYER

(211) 31 TRENCH

(212) 32 GATE INSULATING FILM

(213) 33 GATE ELECTRODE

(214) 34 SOURCE ELECTRODE

(215) 35 DRAIN ELECTRODE

(216) 36 DRAIN REGION

(217) 37 DRAIN ELECTRODE (SECOND MAIN SURFACE)

(218) 38 DRAIN REGION (SECOND MAIN SURFACE)

(219) 51 MOSFET

(220) 100 SEMICONDUCTOR SUBSTRATE

(221) 111 p.sup.+ LAYER

(222) 112 n.sup.+ LAYER

(223) G GATE

(224) S SOURCE

(225) D DRAIN

(226) A ANODE

(227) K CATHODE

(228) C1, C1a, C1b, C1c, C1d, C1e, C2, C2a, C2b, C2c, C2d, C2e, C2f, C2g, C2h, C2i, C2j, C3, C3a, C3b, C4, C5, C6, C7, C7a, C7b, C7c, C7d, C7e, C8, C9, C9a, C9b, C9c, C9d, C9e, C10, C11, C12, C13, C14, C41, C41a, C41b, C41c, C41d, C41e, C41f, C41g, C41h, C41i, C41j, C42, C43, C44, C44a, C44b, C44c, C44d, C44e, C45, C45a, C45b, C45c, C45d, C45e, C46 CAPACITOR