The disclosure relates to a complementary field effect transistor (CFET) structure. The CFET structure comprises: a vertical wall structure; a first transistor structure comprising one or more first channel layers; and a second transistor structure comprising one or more second channel layers, wherein the second transistor structure is stacked on the first transistor structure; wherein the first and the second transistor structure are arranged on one side of the vertical wall structure, and wherein the first and the second channel layers are in contact with a side surface of the vertical wall structure. The vertical wall structure comprises: a conductive core layer and a spacer layer which partially covers the conductive core layer on the side surface of the vertical wall structure, wherein the spacer layer has at least one opening to electrically connect the second transistor structure with the conductive core layer.

A semiconductor device includes a stacked transistor structure having field effect transistors on two vertically stacked levels. An interdevice region is disposed between the two vertically stacked levels. A first power line is disposed within the interdevice region, and a second power line is disposed within the interdevice region and vertically spaced from the first power line.

A semiconductor device includes a first circuit cell, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first circuit cell includes a first active area in a first well in a substrate, a second active area in a second well in the substrate, and a first gate structure wrapping around nanostructures in the first active area and the second active area. The first dielectric layer is over the first well. The second dielectric layer is over the first well and the second well. The third dielectric layer is over the second well. The first dielectric layer, the second dielectric layer, and the third dielectric layer are under and in contact with the first gate structure. A thickness of the second dielectric layer is less than thicknesses of the first dielectric layer and the third dielectric layer.

A semiconductor device may include a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate, a device isolation layer between the first and second active patterns, a first source/drain pattern disposed on the first active pattern, a second source/drain pattern disposed on the second active pattern, a first active contact disposed on the first and second source/drain patterns, a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern and extended into a space between the first active contact and the device isolation layer, and an air gap interposed between the first active contact and the barrier pattern. The first active contact may be electrically connected to the first and second source/drain patterns.

A chip includes a first diffusion region extending in a first direction, and a second diffusion region extending in the first direction, wherein the first diffusion region and the second diffusion region are stacked in a second direction perpendicular to the first direction. The chip also includes a first track extending in the first direction above the first diffusion region and a second track extending in the first direction below the second diffusion region. The chip also includes a first topside contact coupled between a first top surface of the first diffusion region and the first track, a first backside contact coupled between a first bottom surface of the second diffusion region and the second track, and a vertical connector coupled between the first track and the second track.

Provided is a semiconductor device including: a first fin structure extending in a vertical direction; a second fin structure extending in the vertical direction, wherein the second fin structure is spaced apart from the first fin structure; an etch stop pattern between the first fin structure and the second fin structure; a lower insulating layer in contact with a lower surface of the first fin structure, a lower surface of the second fin structure and a lower surface of the etch stop pattern; a device isolation layer including an interposed portion on the etch stop pattern, between the first fin structure and the second fin structure; a gate electrode overlapping the interposed portion and the first fin structure; a channel structure overlapping the gate electrode; and a source/drain pattern connected to the channel structure. The etch stop pattern includes a different insulating material from the device isolation layer.

Provided is a semiconductor device including a substrate, a lower power line disposed on a lower portion of the substrate, a channel pattern, on the substrate, including a plurality of semiconductor patterns spaced apart from each other and stacked, a source/drain pattern connected to the channel pattern, a gate electrode between the substrate and each of the plurality of semiconductor patterns, and a rear surface filler structure penetrating the substrate to be disposed under the gate electrode. The rear surface filler structure includes a first filler pattern adjacent to the gate electrode, and a second filler pattern disposed under the first filler pattern. The first filler pattern covers an upper surface of the second filler pattern and a portion of each of side surfaces of the second filler pattern.

A semiconductor device may include a first impurity pattern and a second impurity pattern spaced apart from each other in a first direction on a substrate, where the first direction may be parallel to an upper surface of the substrate and where the first and second impurity patterns may include impurities having different conductive types; a first semiconductor pattern between the first impurity pattern and the second impurity pattern; and a first gate pattern crossing the first semiconductor pattern. The first gate pattern may include a gate region and an extension region. The gate region may extend in a second direction, which may cross the first direction. The extension region may extend from the gate region in the first direction.

A semiconductor device includes a substrate, a first lower pattern on the substrate, and an element isolation film on the substrate and surrounding at least parts of sidewalls of the first lower pattern, wherein at least part of an upper surface of the first lower pattern is inclined relative to an upper surface of the substrate.

Provided is a cell architecture for a semiconductor device, which includes: at most thee frontside signal tracks provided at a same level on a front side of a semiconductor cell and extended in a 1.sup.st direction in parallel with a 1.sup.st boundary or a 2.sup.nd boundary of the semiconductor cell, the 1.sup.st boundary facing the 2.sup.nd boundary in a 2.sup.nd direction intersecting the 1.sup.st direction; at least one backside signal track provided on a back side of the semiconductor cell and extended in the 1.sup.st direction; and at least one signal line provided in at least one of the at most three frontside signal tracks and the at least one backside signal track and connected to at least one front-end-of-line (FEOL) structure or at least one middle-of-line (MOL) structure in the semiconductor cell, wherein the at most three frontside signal tracks are arranged in the 2.sup.nd direction with a predetermined pitch, and wherein a sum number of the at most three frontside signal tracks and the at least one backside signal track is four.