A semiconductor device may include a substrate including a first well region comprising an impurity of a first conductivity type, first active patterns on the first well region and spaced apart from each other in a first direction parallel to a top surface of the substrate, second active patterns on the first well region and spaced apart from each other in the first direction, source/drain patterns on the first active patterns, the source/drain patterns comprising an impurity of a second conductivity type, and first impurity patterns on the second active patterns, the first impurity patterns comprising an impurity of the first conductivity type. A width of a top surface of each of the second active patterns in the first direction may be greater than a width of a top surface of each of the first active patterns in the first direction.

A semiconductor device including a transistor on a substrate, the transistor including a conductive pattern; a first metal layer on the transistor, the first metal layer including a first wiring line and a first via below the first wiring line; and an etching stop layer between the transistor and the first metal layer. The first via penetrates the etching stop layer and connects the conductive pattern and the first wiring line. The first via includes a first barrier pattern, a second barrier pattern on the first barrier pattern, and a side barrier pattern between the second barrier pattern and the etching stop layer. The side barrier pattern includes a transition metal oxide.

There is provided a semiconductor device capable of improving element performance and the degree of integration of elements by forming an alignment mark that may prevent misalignment in a photo process. The semiconductor device includes a base film, a plurality of lower alignment insulating patterns disposed on the base film, and an upper alignment insulating pattern disposed on the lower alignment insulating patterns, extending in a first direction, and in direct contact with each of the lower alignment insulating patterns, wherein the lower alignment insulating patterns extend in a second direction perpendicular to the first direction and are spaced apart from each other in the first direction.

Embodiments herein relate to an interconnect architecture for a multi-transistor stack including channel structures in the form of nanoribbons or nanowires. In one aspect, a metal interconnect is routed between the transistors to provide between electrical connections for control gates and/or source/drain nodes of the transistors. The electrical connections can be provided between transistors in the same stack or in different stacks. In another aspect, control gates of transistors in a stack are independently controlled.

An integrated circuit device includes a first stack of active-region structures extending in a first direction and including a lower and upper active-region structures stacked with each other; a front-side power rail extending in an upper conductive layer above the lower and upper active-region structures; a back-side power rail extending in a lower conductive layer below the lower and upper active-region structures; an array of vertical power lines each extending in a second direction in a conductive layer different from the upper conductive layer and the lower conductive layer, the second direction being perpendicular to the first direction; and a filler cell having therein a segment of the first stack of active-region structures and having therein a power via-connector which extends in the third direction and conductively connects the front-side power rail with the back-side power rail, and wherein the filler cell is between two of the vertical power lines.

A multi-stack semiconductor device includes: a 1.sup.st active pattern extending in a 1.sup.st direction; a 2.sup.nd active pattern extending in the 1.sup.st direction, the 2.sup.nd active pattern being above the 1.sup.st active pattern in a 3.sup.rd direction which intersects the 1.sup.st direction and a 2.sup.nd direction intersecting the 1.sup.st direction; and a plurality of gate structures extending in the 2.sup.nd direction and arranged in the 1.sup.st direction, wherein at least one of the 1.sup.st active pattern and the 2.sup.nd active pattern has a width in the 2.sup.nd direction which varies along the 1.sup.st direction.

A semiconductor device according to an embodiment of the present disclosure includes: a substrate that includes a first surface and a second surface facing each other and includes a first device region and a second device region at which different conductivity types of devices are disposed; a first channel pattern and a second channel pattern that are each disposed above the first surface of the substrate at the first device region and the second device region; an insulating structure that extends in a first direction between the first device region and the second device region; gate structures that surround the first channel pattern and the second channel pattern and extend in a second direction intersecting the first direction; source/drain patterns that are connected to both sides of each of the first channel pattern and the second channel pattern; a lower wire that is disposed on the second surface of the substrate and is connected to at least some of the source/drain patterns and the gate structure disposed at one edge of the first device region; and a device separation film that penetrates the gate structure disposed at the other edge of the first device region.

A semiconductor device includes a substrate including a first active pattern and a second active pattern that are spaced apart from each other in a first direction that is parallel to a top surface of the substrate, a first source/drain pattern on the first active pattern, a second source/drain pattern on the second active pattern, a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, and a cutting pattern between the first active contact and the second active contact, where the cutting pattern may include a first cutting pattern between the first active contact and the second active contact, the first cutting pattern extending toward the substrate, and a second cutting pattern on at least one lateral surface of the first cutting pattern and a bottom surface of the first cutting pattern, the second cutting pattern exposing at least a portion of the at least one lateral surface of the first cutting pattern.

A semiconductor structure is provided. The semiconductor structure includes a transistor, a contact and a power supply line. The transistor includes a gate structure having a plurality of semiconductor layers extending along a first direction and vertically stacked along a second direction in a device region, and a first source/drain region and a second source/drain region on opposite sides of the gate structure. The contact is formed on a back-side of the first source/drain region. The power supply line is formed on a back-side of the device region and electrically connected to the contact. A first dielectric layer is in contact with sidewall of the contact, and the first dielectric layer extends from the power supply line to contact the first source/drain region. A second dielectric layer is in contact with sidewall of the first dielectric layer close to the power supply line.