A display device includes a bank pattern disposed on a substrate, a first electrode pattern disposed on the bank pattern, a light-emitting element disposed on the first electrode pattern to be electrically connected to the first electrode pattern, a second electrode pattern configured to cover the light-emitting element, an inorganic insulating layer configured to cover the bank pattern, the first electrode pattern, and the light-emitting element between the first electrode pattern and the second electrode pattern, and a diffusion layer which includes a plurality of diffusion particles and is in contact with the inorganic insulating layer.

A method for manufacturing a light-emitting device includes preparing a wafer in which multiple semiconductor parts are arranged on a first surface of a first substrate, disposing a resin member covering the first surface and the multiple semiconductor parts, disposing a second substrate on the resin member, removing the first substrate, forming a dielectric layer continuously covering upper surfaces of the multiple semiconductor parts and an upper surface of the resin member, causing an upper surface of the dielectric layer to approach flat, selectively removing the dielectric layer located on the upper surface of the resin member, and directly bonding a wavelength conversion member to the upper surface of the dielectric layer.

A display device includes a substrate having a pixel electrode, a light emitting element disposed on the pixel electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer, a step coverage prevention layer surrounding the light emitting element in a plan view, a common electrode disposed on the light emitting element and the step coverage prevention layer, and an oxidation prevention layer disposed on a portion of the common electrode that does not overlap the light emitting element in a thickness direction. The common electrode includes a first portion disposed on the light emitting element and a second portion disposed between the oxidation prevention layer and the step coverage prevention layer, and a material forming the first portion is an oxide of a material forming the second portion.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A micro light-emitting diode and a preparation method therefor, a micro light-emitting element and a display. The micro light-emitting diode comprises an epitaxial layer and a dielectric layer, wherein the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are arranged in sequence, and has a first surface and a second surface which are arranged opposite each other, the first semiconductor layer being located on the side of the epitaxial layer close to the first surface; the epitaxial layer is configured with a mesa, and the mesa is exposed from the first semiconductor layer and faces the second surface; and the dielectric layer covers the first surface and at least part of a side wall of the epitaxial layer, and the height H.sub.1 of the dielectric layer on the side wall of the epitaxial layer is less than the height of the mesa.

In an embodiment an optoelectronic component with an epitaxial layer sequence comprises a functional inner region having a first electrical contact and a second electrical contact opposite the first electrical contact, as well as semiconductor layers arranged between the first electrical contact and the second electrical contact configured to generate light. The semiconductor layers comprise a base area that increases towards the second electrical contact. A dielectric passivation layer is arranged on the side walls of the semiconductor layers. A mirror layer surrounds the passivation layer at a distance thereby forming a gap. The second electrical contact and a plane of the gap surrounding the second electrical contact form a common light-emitting surface.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit; in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

A light emitting diode (LED) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on a portion of the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the first semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulating layer overlapping the first semiconductor layer, the second semiconductor layer, and the reflection pattern, in which the insulating layer has a first region having different thicknesses and a second region having a substantially constant thickness.

Disclosed are a light emitting diode and a light emitting diode module. The light emitting diode module includes a printed circuit board and a light emitting diode joined thereto through a solder paste. The light emitting diode includes a first electrode pad electrically connected to a first conductive type semiconductor layer and a second electrode pad connected to a second conductive type semiconductor layer, wherein each of the first electrode pad and the second electrode pad includes at least five pairs of Ti/Ni layers or at least five pairs of Ti/Cr layers and the uppermost layer of Au. Thus a metal element such as Sn in the solder paste is prevented from diffusion so as to provide a reliable light emitting diode module.

There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.