A light emitting diode chip includes: a first conductive type semiconductor layer disposed on a substrate; a mesa disposed on the first conductive type semiconductor layer and including an active layer and a second conductive type semiconductor layer; an insulation layer covering the first conductive type semiconductor layer and the mesa, the insulation layer including at least one first opening exposing the first conductive type semiconductor layer and a second opening disposed on the mesa; a first pad electrode disposed on the insulation layer and electrically connected to the first conductive type semiconductor layer through the first opening; and a second pad electrode disposed on the insulation layer and electrically connected to the second conductive type semiconductor layer through the second opening. The first opening of the insulation layer includes a first region covered by the first pad electrode and a second region exposed outside the first pad electrode.

A light emitting device includes a support member having a mounting surface. The support member includes an insulating member having top surface and a plurality of side surfaces, a first metal pattern disposed on the top surface of the insulating member, and a second metal pattern disposed on the side surface of the insulating member such that a side surface of the second metal pattern is continuous with a top surface of the first metal pattern. The light emitting device further includes a light emitting element mounted on the mounting surface at a location of the first metal pattern, and a bonding member that bonds the light emitting element to the mounting surface. The bonding member covers at least a portion of the first metal pattern and at least a portion of the second metal pattern.

Semiconductor LED layers are epitaxially grown on a patterned surface of a sapphire substrate. The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact and an n-metal contact. A dielectric polymer stress-buffer layer is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

A light emitting diode (LED) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the second semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulation layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and overlapping the first semiconductor layer, the second semiconductor layer, and the second conductive layer, in which the insulation layer has a first region having different thicknesses and a second region having a substantially constant thickness.

A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element 1 includes a substrate 2, an n-type nitride semiconductor layer 3, a light-emitting layer 4, a p-type nitride semiconductor layer 5, a transparent electrode layer 6 and a reflective electrode layer 7, and the transparent electrode layer 6 has a thickness T satisfying the following expression (1):

[00001]$\begin{array}{cc}\frac{3.Math.}{4.Math.n}+0.30\left(\frac{}{4.Math.n}\right)T\frac{3.Math.}{4.Math.n}+0.45\left(\frac{}{4.Math.n}\right)& \left(1\right)\end{array}$

wherein is the light-emitting wavelength of the light-emitting element 4, and n is the refractive index of the transparent electrode layer 6.

A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.

A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.