A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

A high electron mobility transistor includes: a channel layer through which carriers are to flow; a pair of respective main electrodes coupled to one end and another end of the channel layer; a barrier layer that is disposed at the channel layer and induces the carriers; a gate electrode disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween; a first spacer layer that is disposed between the channel layer and the barrier layer and decreases alloy scattering; and a second spacer layer that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode and traps the carriers.

A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.

A nitride semiconductor device includes: a substrate; a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer disposed above the first semiconductor layer, having a bandgap larger than that of the first semiconductor layer, and undoped; a third semiconductor layer of a second conductivity type disposed above the second semiconductor layer; a fourth semiconductor layer including a channel, and at least partially disposed above the third semiconductor layer; a gate electrode disposed above the first semiconductor layer; a drain electrode disposed below the substrate; and an insulating layer disposed above the gate electrode. The insulating layer covers a bottom and a side wall of a groove provided in an edge termination area of the nitride semiconductor device and penetrating through the third semiconductor layer to reach the second semiconductor layer.

A semiconductor die includes: a silicon-on-insulator (SOI) substrate having a silicon device layer, a bulk silicon substrate, and a buried oxide layer separating the silicon device layer from the bulk silicon substrate; a lateral power MOSFET (metal-oxide-semiconductor field-effect transistor) in a first device region of the silicon device layer; and an additional semiconductor device in a second device region of the silicon device layer and having a lower breakdown voltage than the lateral power MOSFET. The silicon device layer has a first thickness in a first part of the first device region and a second thickness in a second part of the first device region, the second thickness being greater than the first thickness. The silicon device layer has the first thickness throughout the second device region. Additional semiconductor die embodiments are also described.

A semiconductor device includes a substrate, a drift layer, a junction field-effect transistor region, a well region, a source region, and a gate structure. The drift layer is over the substrate. The junction field-effect transistor region is over the drift layer, and a doping concentration of the junction field-effect transistor region decreases as being far away from the substrate. The well region is over the drift layer and at a side of the junction field-effect transistor region. The source region is in the well region. The gate structure is over the junction field-effect transistor region.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first source electrode, a second source electrode, and a drain electrode. The second nitride-based semiconductor layer includes a drift region doped, a first barrier region, and a second barrier region. The first and second barrier regions extend downward from a top surface of the second nitride-based semiconductor layer and are separated from each other by a portion of the drift region. The gate electrode is disposed on the first barrier region. The first source electrode is disposed on the portion of the drift region. The second source electrode is disposed on the second barrier region and is electrically coupled with the first source electrode. The drain electrode is connected to the first nitride-based semiconductor layer.

A transistor having a drain layer formed within a substrate. A drift layer formed over the drain layer, the drift layer having a recessed portion and a protruding portion with a tee-shaped portion. A well layer formed over the recessed portion of the drift layer. A body layer formed over a first portion of the well layer. A source layer formed over a second portion of the well layer. A JFET layer formed within the tee-shaped portion of the drift layer. An insulating layer formed over a portion of the source layer, over a fourth portion of the well layer along the sides of the protruding portion of the drift layer, and over the tee-shaped portion of the drift layer. A gate electrode formed over the insulating layer.

A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.

A semiconductor device includes a semiconductor element configured to form an upper-lower arm circuit of a power conversion device. The semiconductor element includes a control electrode, a high-potential electrode and a low-potential electrode. A parasitic capacitance between the control electrode and the high-potential electrode changes according to a potential difference between the high-potential electrode and the low-potential electrode. A value of the parasitic capacitance at a time when the potential difference is equal to 80 percent of a breakdown voltage of the semiconductor element is defined as a first capacitance value. An arbitrary value of the parasitic capacitance at a time when the potential difference is in an inclusive range of 20 percent to 40 percent of the breakdown voltage is defined as a second capacitance value. The first capacitance value is larger than the second capacitance value.