A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer, and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

Disclosed are a lateral silicon carbide junction gate field effect transistor (SiC-JFET) device and a manufacturing method thereof. The lateral SiC-JFET device includes a base; a source and a drift region formed on the base in sequence; a first source contact region, a second source contact region, and a channel region formed on the source in sequence; and a gate formed on the channel region; where the channel region and the drift region are independent structures respectively. The embodiments of the present disclosure solved the technical problem that the adjustment of the breakdown voltage of the conventional lateral SiC-JFET device is limited by the size of the channel region.

A junction field effect transistor device includes a substrate, a well region, a first top layer, a plurality of source/drain regions, a first isolation structure, a gate, and a plurality of first well slots. The substrate has a first conductivity type. The well region is embedded in the substrate. The well region has a second conductivity type. The first top layer is embedded in the well region. The first top layer has the first conductivity type. The source/drain regions are disposed on a top surface of the well region. The first isolation structure is adjacent to one of the source/drain regions. The gate is disposed on a top surface of the first top layer. The first well slots are disposed below the gate. A second-conductivity-type dopant concentration of the first well slots is lower than a second-conductivity-type dopant concentration of the well region.

A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.