A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.

A method of manufacturing a junction field effect transistor having a channel region disposed in a semiconductor substrate, deeper than one of a source region and a drain region, the method includes a first step of forming a first mask having a first opening portion over the semiconductor substrate in which a first semiconductor region of a first conductivity type is disposed, a second step of forming a second semiconductor region of a second conductivity type defined as the channel region, in the first semiconductor region by implantation of ions of second conductivity type opposite to the first conductivity type using the first mask, and a third step of forming a third semiconductor region of the second conductivity type defined as the one of the source region and the drain region, by implantation of ions of the second conductivity type, using the first mask.

A transistor device includes: a first source region and a first drain region spaced apart from each other in a first direction of a semiconductor body; at least two gate regions arranged between the first source region and the first drain region and spaced apart from each other in a second direction of the semiconductor body; at least one drift region adjoining the first source region and electrically coupled to the first drain region; at least one compensation region adjoining the at least one drift region and the at least two gate regions; a MOSFET including a drain node connected to the first source region, a source node connected to the at least two gate region, and a gate node. Active regions of the MOSFET are integrated in the semiconductor body in a device region that is spaced apart from the at least two gate regions.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.

Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using structures configured to cooperatively control a common semi-conductive channel region (SCR). One embodiment includes providing a metal oxide semiconductor field effect transistor (MOSFET) section formed with an exemplary SCR and two junction field effect transistor (JFET) gates on opposing sides of the MOSFET's SCR such that operation of the JFET modulates or controls current through the MOSFET's. With two JFET gate terminals to modulate various embodiments' signal(s), an improved mixer, demodulator, and gain control element in, e.g., analog circuits can be realized. Additionally, a direct current (DC)-biased terminal of one embodiment decreases cross-talk with other devices. A lens structure can also be incorporated into MOSFET structures to further adjust operation of the MOSFET. An embodiment can also include a current leakage mitigation structure configured to reduce or eliminate current leakage between MOSFET and JFET structures.

The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

The disclosure provides a structure including a silicon carbide (SiC) channel horizontally between a source and a drain drift region. The SiC channel has opposite doping from the source and the drain drift region. A capping semiconductor is on the SiC channel and is horizontally between the source and the drain drift region. The capping semiconductor includes a semiconductor having a higher charge carrier mobility than the SiC channel. A gate structure is on the capping semiconductor.

A semiconductor device includes a substrate, a semiconductor layer provided on the substrate and having a plurality of GaN channel layers and a plurality of AlGaN barrier layers which are alternately laminated from a substrate side, a source electrode and a drain electrode electrically connected to the GaN channel layers, and a gate electrode provided between the source electrode and the drain electrode to control a potential of the semiconductor layer, wherein an Al composition ratio of an AlGaN barrier layer closest to the substrate is smaller than that of an AlGaN barrier layer second closest to the substrate.