One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region.

In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.

A compound semiconductor device includes a channel layer of first arsenide semiconductor, an electron supply layer of second arsenide semiconductor over the channel layer, a gate electrode, a source electrode and a drain electrode over the channel layer, and a metal film between the gate electrode and the drain electrode, the metal film being insulated from the gate electrode and the drain electrode.

A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.

The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.