A semiconductor cell includes a substrate; a buffer structure disposed on the substrate; a channel layer having a band gap, and including a first portion on the buffer structure and a first protrusion which is disposed on the first portion and has a first top surface and a first inclined surface connecting to the first top surface; a barrier having a band gap greater than the band gap of the channel layer, disposed on the channel layer, and including a second portion disposed on the first portion, and a second protrusion covering the first top surface of the first protrusion and having a second top surface and a second inclined surface connecting to the second top surface and parallel to the first inclined surface; a first electrode disposed on the second protrusion; and a second electrode disposed on the second portion of the barrier and separated from the first electrode.

A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.

A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.

A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

The invention relates to a method for forming a device (5) comprising graphene, the method comprising the following steps: a step S1 of forming a graphene film (1) on a substrate (2); a step S2 of depositing, on the graphene film (1), a functionalisation material (3) configured to modify physicochemical properties of the graphene film (1), the deposition of functionalisation material being configured to partially cover the graphene film (1); a step S3 of gas-phase deposition of a polymer material (4) covering the graphene film (1) and the functionalisation material (3); anda step S4 of removing the substrate (2) so that the polymer material (4) forms a support for the graphene film (1).

A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.

According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

A semiconductor device includes a buffer layer, a barrier layer, a nitride-based semiconductor layer, an isolation layer, and a gate electrode. The barrier layer is disposed on the buffer layer. The nitride-based semiconductor layer is disposed on the barrier layer and has a channel region and a doped region abutting against each other. The isolation layer covers the nitride-based semiconductor layer. The isolation layer and doped channel region can exhibit a type-II energy band alignment (staggered gate stack). The gate electrode is disposed over the isolation layer and the nitride-based semiconductor layer.

A system and method for creating layout for standard cells are described. In various implementations, a standard cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The direction of current flow of the top GAA transistor is orthogonal to the direction of current flow of the bottom GAA transistor. The channels of the vertically stacked transistors use opposite doping polarities. The orthogonal orientation allows both the top and bottom GAA transistors to have the maximum mobility for their respective carriers based on their orientation. The Cross FETs utilize a single metal layer and a single via layer for connections between the top and bottom GAA transistors.