A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (m) and satisfies Y(0.2171)ln(X)8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

A transistor comprises a layered semiconductor structure electrically connected to a plurality of electrodes forming a source, a gate, and a drain of the transistor. The layered semiconductor structure includes a channel layer having a shape formed by a set of fins, and a barrier layer on the channel layer such that the barrier layer coats the fins of the channel layer to define a shape formed by a series of wells. The series of wells of the barrier layer are interdigitated with the series of fins of the channel layer. The barrier layer is formed with polar piezoelectric material having a first lattice constant and the channel layer is formed with polar material having a second lattice constant, where the second lattice constant is greater than the first lattice constant.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (W.sub.eff) Z, then the second logic cell has a height 2X, a width Y, and W.sub.eff>2.5 Z.

A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.

A semiconductor device according to embodiments of the present invention is a field-effect transistor including a gate electrode between a source electrode and a drain electrode, wherein carriers travel between the source electrode and the drain electrode, a channel control layer is provided between a channel through with the carriers travel and the gate electrode, a recess is disposed at least in part of a surface in contact with the gate electrode on a source electrode side in the channel control layer, and a part of the gate electrode is filled in the recess.

A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (um) and satisfies Y(0.2171)ln(X)8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.