A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.

A high bandgap Schottky contact layer device and methods for producing same are provided herein. According to one aspect, a high bandgap Schottky contact layer device comprises a substrate, a first Schottky layer over the substrate, the first Schottky layer having a first bandgap, and a second Schottky layer over the first Schottky layer, the second Schottky layer having a second bandgap. The device further comprises a first metal contact over the second Schottky layer and at least one ohmic contact, a portion of which being in direct contact with the substrate. The first bandgap is greater than 1.7 electronvolts (eV). In one embodiment, the second bandgap is also greater than 1.7 eV.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals. The second Ill-nitride semiconductor region includes a second heterojunction, a third terminal connected to the second Ill-nitride semiconductor region, a fourth terminal laterally spaced from the third terminal and connected to the second Ill-nitride semiconductor region, first highly doped semiconductor regions of a first conductivity type formed over the second Ill-nitride semiconductor region.

A high-electron mobility transistor includes a semiconductor body including a barrier region, a channel region, and a two-dimensional charge carrier gas channel, first and second electrodes that are each in electrical contact with the two-dimensional charge carrier gas channel, and a gate structure laterally in between the first and second electrodes, wherein the gate structure comprises a gate electrode and a first region of doped type III-V semiconductor material in between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of doped type III-V semiconductor material comprises a plurality of side faces that define a plan view geometry of the first region, and wherein in the plan view geometry of the first region at least two lateral boundaries of the first region that intersect one another extend along crystallographically equivalent planes of the doped type III-V semiconductor material.

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first transistor disposed on the main surface, a second transistor disposed on the main surface, a third transistor disposed on the main surface between the first transistor and the second transistor, a first gate line disposed on the main surface, and a back-surface metal layer disposed on the back surface.

A semiconductor device includes a substrate having a main surface and a back surface, and first and second transistors. A first gate wiring is provided on the main surface a disposed in a first source electrode of the first transistor when viewed from a direction, and is electrically connected to a first gate electrode thereof. The second source electrode is interposed between a second gate electrode of the second transistor and a first gate wiring. A back metal layer is provided on the back surface and is electrically connected to the first source electrode and a second source electrode of the second transistor through a first via hole and a second via hole which overlap the first source electrode and the second source electrode, respectively, when viewed in a thickness direction of the substrate.

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.