The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of field effect transistors, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.

In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

An n.sup. drift region is disposed on the front surface of an n.sup.+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n.sup. drift region. A high-concentration p.sup.+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n.sup. drift region. Inside the high-concentration p.sup.+ base region, an n.sup.+ high-concentration region is selectively disposed at the n.sup.+ semiconductor substrate side. The n.sup.+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p.sup.+ base regions line up. The n.sup.+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n.sup.+ semiconductor substrate side of the n.sup.+ high-concentration region adjoins the part sandwiched between the high-concentration p.sup.+ base region and the n.sup.+ semiconductor substrate in the n.sup. drift region.

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and an insulating portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is located in a vicinity of, and contacts, the second semiconductor region and the third semiconductor region, and the insulating portion includes a plurality of voids therein, the plurality of voids extending around the second semiconductor region.

A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

An electronic device, includes: a graphene nanoribbon having a first graphene and a second graphene; a first electrode coupled to the first graphene; and a second electrode coupled to the second graphene, wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity and the second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity.

The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case.

A method includes forming, on a dielectric layer of an integrated circuit, a first layer of a first material, forming, on the first layer, a second layer of a second material, and patterning the second layer to expose the first layer. Via the patterned second layer, the exposed first layer is etched to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures. The method also includes forming a graphitic carbon layer on at least part of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.