Various solid-state circuit breakers and related circuits are presented herein. These include, among other things, a common node bidirectional solid-state circuit breaker (BDSSCB) having diodes connected between terminals of its switches, a shunt voltage actuated driver (SVAD) circuit for use with a BDSSCB, a SVAD circuit for use with a unidirectional solid-state circuit breaker (UDSSCB), a bipolar current actuated driver (BCAD) for use with a BDSSCB, and a multi-directional solid-state circuit breaker (MDSSCB).

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

A method for coating a substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The plasma ball has a diameter. The plasma ball is disposed at a first distance from the substrate and the substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the substrate, and a diamond coating is deposited on the substrate. The diamond coating has a thickness. Furthermore, the diamond coating has an optical transparency of greater than about 80%. The diamond coating can include nanocrystalline diamond. The microwave plasma source can have a frequency of about 915 MHz.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

In various embodiments, a method of forming a graphene structure is provided. The method may include forming a body including at least one protrusion, and forming a graphene layer at an outer peripheral surface of the at least one protrusion.

In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

A semiconductor device includes a MISFET having: a diamond substrate; a drift layer having a first layer with a first density for providing a hopping conduction and a second layer with a second density lower than the first density, and having a dope structure; a body layer on the drift layer; a source region in an upper portion of the body layer; a gate insulation film on a surface of the body layer; a gate electrode on a surface of the gate insulation film; a first electrode electrically connected to the source region and a channel region; and a second electrode electrically connected to the diamond substrate. The MISFET flows current in the drift layer in a vertical direction, and the current flows between the first electrode and the second electrode.

The present invention relates to a method for manufacturing a transistor according selective printing of a dopant. For the manufacture of a transistor, a semiconductor layer is formed on a substrate, and a dopant layer is formed on the semiconductor layer. In the formation of the dopant layer, an inkjet printing is used to selectively print an n type dopant or a p type dopant.