The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region.

A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

A method of forming a graphite-based structure on a substrate comprises patterning the substrate thereby forming a plurality of elements on the substrate. Each respective element in the plurality of elements is separated from an adjacent element on the substrate by a corresponding trench in a plurality of trenches on the substrate and each respective element in the plurality of elements has a corresponding top surface. The method further comprises segmentedly depositing a graphene initiating layer onto the top surface of each respective element in the plurality of elements; and generating graphene using the graphene initiating layer thereby forming the graphite-based structure.

In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power semiconductor chip, a plurality of collector main terminals and a plurality of emitter main terminals electrically connected to the power semiconductor chip, and a signal line. The plurality of collector main terminals and the plurality of emitter main terminals have protrusion portions which protrude from a disposition surface of the power semiconductor chip, respectively, and the signal line surrounds, with respect to these protrusion portions, an entire circumference of all the protrusion portions and is spaced apart therefrom in plan view.

A multilayer graphene, a method of forming the same, a device including the multilayer graphene, and a method of manufacturing the device are provided. In the method of forming the multilayer graphene, a first graphene is formed on an underlayer, and then a multilayer graphene is formed by exposing two adjacent areas on the first graphene to a source gas. By differentiating temperatures and source gasses, the multilayer graphene has different electrical characteristics in the two adjacent areas.

A semiconductor device includes a first conductivity type semiconductor layer that includes a wide bandgap semiconductor and a surface. A trench, including a side wall and a bottom wall, is formed in the semiconductor layer surface, and a Schottky electrode is connected to the surface. Opposite edge portions of the bottom wall of the trench each include a radius of curvature, R, satisfying the expression 0.01 L<R<10 L, where L represents the straight-line distance in a width direction of the trench between the opposite edge portions.

Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.

Example embodiments relate to an electronic device having a graphene-semiconductor multi-junction and a method of manufacturing the electronic device. The electronic device includes a graphene layer having at least one graphene protrusion and a semiconductor layer that covers the graphene layer. A side surface of each of the at least one graphene protrusion may be uneven, may have a multi-edge, and may be a stepped side surface. The graphene layer includes a plurality of nanocrystal graphenes. The graphene layer includes a lower graphene layer having a plurality of nanocrystal graphenes and the at least one graphene protrusion that is formed on the lower graphene layer. The semiconductor layer may include a transition metal dichalcogenide (TMDC) layer. Each of the at least one graphene protrusion may include a plurality of nanocrystal graphenes.