A method is provided for operating a fractional quantum Hall apparatus including a set of interferometers, each having a cell and a set of gate electrodes located around the cell. The method includes calibrating each one of the interferometers to confine a droplet of a 2D charge carrier gas in a fractional quantum Hall effect state of filling factor 17/5 or 12/5, while a reentrant phase of integer quantum Hall effect states of the 2D charge carrier gas is located between the area of the droplet in a fractional quantum Hall effect state and the interferometer electrodes. The calibrating includes setting a value of a magnetic field across the apparatus such that the reentrant phase and the droplet of the 2D charge carrier gas are present in at least one of the interferometers based on interference measurements on at least one of the interferometers for different values of the magnetic field.

According to one embodiment, a nitride structure includes a base, a nitride member including Ga and N, and a stacked structure provided between the base and the nitride member in a first direction. The stacked structure includes a plurality of high composition films including Al.sub.x1Ga.sub.1-x1N (0<x11), and a plurality of low composition films including Al.sub.x2Ga.sub.1-x2N (0x2<1, x2<x1). A high composition film thickness of one high composition film is thinner than a nitride member thickness of the nitride member in the first direction. A low composition film thickness of one of the plurality of low composition films in the first direction is thinner than the nitride member thickness. The high composition film and the low composition film are provided alternately along the first direction. The plurality of high composition films includes a first film and another film.

In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A 3D micro-curved epitaxial functional structure comprises a base layer that includes, from bottom to top, at least a sapphire substrate layer and a first epitaxial layer. A mask layer is located above the base layer, with spaced grooves that extend through it and expose the upper surface of the base layer. Multiple 3D micro-curved epitaxial structural units are formed, each with its bottom part filling a corresponding groove and its upper surface exhibiting a smooth 3D curved structure. Each 3D micro-curved epitaxial structural unit is partially in contact with the upper surface of the mask layer. By introducing an excess of Ga source while adjusting the crystal plane orientation angle during wet etching with Sc source, multiple epitaxial growth processes are performed to form the 3D micro-curved epitaxial functional structure, achieving compatibility with chip epitaxial processes and providing technical feasibility for creating complex structures.

A base structure and a method for manufacturing the base structure, and a semiconductor device are provided. The base structure includes a substrate and a Group III-V superlattice layer. The Group III-V superlattice layer includes a plurality of lattice stack layers stacked on the substrate. A lattice stack layer includes at least two semiconductor layers, and a semiconductor layer includes a first Group III component and a second Group III component. In a same lattice stack layer, a proportion of the first Group III component in a semiconductor layer away from the substrate is less than a proportion of the first Group III component in a semiconductor layer proximate to the substrate. The Group III-V superlattice layer can effectively achieve structural relaxation between the substrate and an epitaxial structure, reduce dislocation density in the epitaxial structure and improve a performance of a device manufactured on the epitaxial structure.

The techniques described herein relate to a transistor including a single crystal substrate, an epitaxial channel layer (ECL) on the single crystal substrate, a gate layer on the ECL, a source electrical contact coupled to the ECL, a drain electrical contact coupled to the ECL, and a gate electrical contact coupled to the gate layer. The substrate includes a substrate material with a first crystal symmetry and the ECL includes an ECL oxide material with a second crystal symmetry, where the first crystal symmetry is different from the second crystal symmetry. The gate layer includes a gate oxide material, where the ECL oxide material has a first bandgap and the gate oxide material has a second bandgap, and the second bandgap is wider than the first bandgap.