A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.

A method is provided for operating a fractional quantum Hall apparatus including a set of interferometers, each having a cell and a set of gate electrodes located around the cell. The method includes calibrating each one of the interferometers to confine a droplet of a 2D charge carrier gas in a fractional quantum Hall effect state of filling factor 17/5 or 12/5, while a reentrant phase of integer quantum Hall effect states of the 2D charge carrier gas is located between the area of the droplet in a fractional quantum Hall effect state and the interferometer electrodes. The calibrating includes setting a value of a magnetic field across the apparatus such that the reentrant phase and the droplet of the 2D charge carrier gas are present in at least one of the interferometers based on interference measurements on at least one of the interferometers for different values of the magnetic field.

The techniques described herein relate to a transistor including a substrate including sapphire, an epitaxial channel layer on the substrate, and an epitaxial gate layer on the channel layer. The epitaxial channel layer can include -Ga.sub.2O.sub.3, with a first bandgap. The epitaxial gate layer can include an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts, including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the epitaxial gate layer.

A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.1 for intersubband transition energies greater than 1.0 eV, and/or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.4 nm.sup.1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The plurality of first semiconductor layers can comprise a first short-period superlattice (SPSL). The chirp layer can comprise alternating layers of GaN layers and AlN layers. An average composition of Al/(Al+Ga) of the chirp layer changes throughout the chirp layer.

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

A trench field effect transistor (TFET) may include a semiconductor layer having a trench therein, and a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The TFET may further include source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.

A superjunction superlattice semiconductor device and a method of making the same are presented. In embodiments, the method includes: growing, on a substrate, alternating n-type and p-type semiconductor layers in the plane of the substrate, thereby forming a superjunction region providing a depletion effect; etching opposing sides of the superjunction region and the substrate to form spaced first and second sloped sidewalls, wherein each of the first and second sloped sidewalls extend at an oblique angle with respect to a top surface of the substrate; forming a first metal contact in communication with the first sidewall; and forming a second metal contact in communication with the second sidewall.