Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

An insulated gate bipolar transistor includes: a drift layer having a semiconductor substrate with N-type conductivity; a collector layer having P-type conductivity at a surface layer of the semiconductor substrate at a back surface side; and a field stop layer between the drift layer and the collector layer that has a higher impurity concentration than the drift layer. In a thickness direction of the semiconductor substrate, a lifetime control layer is arranged with a predetermined half value width by helium ion implantation; and the field stop layer is arranged with a predetermined half value width by hydrogen ion implantation. Further, a half value width region of the lifetime control layer and a half value width region of the field stop layer overlap each other.

A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.

A method for forming a bipolar semiconductor switch includes providing a semiconductor body which has a main surface, a back surface arranged opposite to the main surface, and a first semiconductor layer, and reducing a charge carrier life-time in the semiconductor body. The charge carrier life-time is reduced by at least one of indiffusing heavy metal into the first semiconductor layer, implanting protons into the first semiconductor layer and implanting helium nuclei into the first semiconductor layer, so that the charge carrier life-time has, in a vertical direction which is substantially orthogonal to the main surface, a minimum in a lower n-type portion of the first semiconductor layer where a concentration of n-type dopants is substantially close to a maximum.

A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.

A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed.

Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration.

A method of manufacturing a semiconductor device includes preparing a light ion source, a first mask and a second mask. A side of a first region on a top surface of a semiconductor substrate is shielded by using the first mask. The top surface, with the side of the first region thereon being shielded with the first mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on a side of a second region on the top surface. A side of the second region on a bottom surface of the semiconductor substrate is shielded by using the second mask. The bottom surface, with the side of the second region thereon being shielded with the second mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on the side of the first region on the bottom surface.

A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.