A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.

A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.

A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.

According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.

There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region.

A method for manufacturing a semiconductor device includes: digging first and second trenches at the top surface of a plate-like base-body portion; forming an insulating film in the inside of each of the first and second trenches;

laminating a conductive film on the top surface of the base-body portion so as to bury the first and second trenches with the conductive film via the insulating film; testing insulation-characteristics of the insulating film by applying a voltage between the conductive film and the bottom surface of the base-body portion; and after testing the insulation-characteristics, selectively removing the conductive film from the top surface of the base-body portion, so as to define a gate electrode in the first trench and an separated-electrode in the second trench, the separated-electrode being separated from the gate electrode.

A p-layer on a surface layer of one of n.sup. drift layers is separated into a p-base-region and a floating p-region by a plurality of trenches. A first gate electrode is disposed on a side wall of the trench on the p-base-region side via a first insulation film, and a shield electrode is disposed on a side wall of the trench on the floating p-region side via a second insulation film. Between the first gate electrode conductively connected to a gate runner via a contact plug embedded in a first contact hole and the shield electrode conductively connected to an emitter electrode via a contact plug embedded in a second contact hole, an insulation film reaches from the front surface of the substrate to the bottom surface of the trench. Hence, the fabrication process can be shortened to provide a highly reliable semiconductor device with low switching loss.

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.