A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion. A majority of dopants within the first drift region portion are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer. Further, a majority of &pants within the second drift region portion are a second species of dopants. Additionally, the semiconductor device includes a trench extending from a surface of the semiconductor layer into the semiconductor layer. A vertical distance of a border between the first drift region portion and the second drift region portion to the surface of the semiconductor layer is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench.

A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer. A gate dielectric is formed at least along sidewalls of the gate trench. After removing the passivation layer, dopants are implanted through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer.

A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.

A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.

A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.

A semiconductor device for restraining snapback is provided. The semiconductor device includes IGBT and diode regions. In a view of n-type impurity concentration distribution along a direction from a front surface to a rear surface, a local minimum value of an n-type impurity concentration is located at a border between cathode and buffer regions. A local maximum value of n-type impurity concentration is located in the buffer region. At least one of the buffer and cathode regions includes a crystal defect region having crystal defects in a higher concentration than a region therearound. A peak of a crystal defect concentration in a view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value.

Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. One or more heavily doped regions of the second conductivity type are formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the substrate. This abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

A semiconductor device is operated by applying a gate voltage with a first value to a gate electrode terminal such that current flows through the IGBT between first and second electrode terminals and current flow through a desaturation channel is substantially blocked. A gate voltage with a second value is applied to the gate electrode terminal the absolute value of which is lower than that of the first value, such that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal. A gate voltage with a third value is applied to the gate electrode terminal, the absolute value of which is lower than that of the first and second values, such that current flow through the IGBT between the first and second electrode terminals is substantially blocked.