Semiconductor device and method of manufacturing the semiconductor device

Abstract

A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.

Claims

1. A semiconductor device comprising: a semiconductor substrate; an upper electrode formed on a top surface of the semiconductor substrate; a lower electrode formed on a bottom surface of the semiconductor substrate; and a gate electrode, wherein an emitter region, a body region, a pillar region, a barrier region, a drift region, a collector region and a cathode region are formed in the semiconductor substrate, the emitter region has an n-type impurity and is connected to the upper electrode, the body region has a p-type impurity, is formed on a lateral side and on a lower side of the emitter region, and is connected to the upper electrode, the pillar region has an n-type impurity, is formed on a lateral side of the body region, extends along a depth from the top surface of the semiconductor substrate to a lower end of the body region, is connected to the upper electrode, and is separated from the emitter region by the body region, the barrier region has an n-type impurity, is formed on a lower side of the body region and the pillar region, and is separated from the emitter region by the body region, the drift region has an n-type impurity, is formed on a lower side of the barrier region, is separated from the emitter region by the barrier region, and has an n-type impurity concentration lower than an n-type impurity concentration in the pillar region and the barrier region, the collector region has a p-type impurity, is formed on a lower side of the drift region, is connected to the lower electrode, and is separated from the barrier region by the drift region, the cathode region has an n-type impurity, is formed on the lower side of the drift region, is connected to the lower electrode, is separated from the barrier region by the drift region, and has an n-type impurity concentration higher than the n-type impurity concentration in the drift region, a trench that penetrates through the emitter region, the body region and the barrier region and reaches the drift region is formed on the top surface of the semiconductor substrate, an inner surface of the trench is covered with a gate insulating film, the gate electrode is disposed in the trench, an n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region is arranged in a curved line which has a peak in the depth direction and has a maximum value in the pillar region, and the n-type impurity concentration distribution has a folding point on a side deeper than the maximum value in the pillar region and shallower than a border of the barrier region and the drift region in the depth direction.

2. The semiconductor device according to claim 1, wherein the n-type impurity concentration distribution has a maximum value in the barrier region.

3. The semiconductor device according to claim 1, wherein a p-type lower body region is formed between the barrier region and the drift region, and the lower body region separates the barrier region and the drift region, is separated from the body region by the barrier region, and is separated from the collector region and the cathode region by the drift region.

4. The semiconductor device according to claim 1, wherein an average value of a p-type impurity concentration in the pillar region is less than 110.sup.15 atoms/cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Features, advantages, and technical and industrial significance of exemplary embodiments of the invention will be described below with reference to the accompanying drawings, in which like numerals denote like elements, and wherein:

(2) FIG. 1 is a vertical cross-sectional view of a semiconductor device 10 of Embodiment 1 of the present invention;

(3) FIG. 2 is a graph that shows impurity concentration distributions in a depth direction in a pillar region 24 and a barrier region 26 on the lower side thereof;

(4) FIG. 3 is a graph that shows distributions of impurities that are implanted in the respective implantation steps in positions corresponding to FIG. 2;

(5) FIG. 4 is a graph that shows impurity concentration distributions corresponding to FIG. 2 in the semiconductor device of Embodiment 2 of the present invention;

(6) FIG. 5 is a graph that shows impurity concentration distributions corresponding to FIG. 3 in the semiconductor device of Embodiment 2 of the present invention;

(7) FIG. 6 is a graph that shows impurity concentration distributions corresponding to FIG. 2 in a semiconductor device of Embodiment 3 of the present invention;

(8) FIG. 7 is a graph that shows impurity concentration distributions corresponding to FIG. 3 in the semiconductor, device of Embodiment 3 of the present invention; and

(9) FIG. 8 is a vertical cross-sectional view of a semiconductor device of Embodiment 4 of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

(10) A semiconductor device 10 of Embodiment 1 shown in FIG. 1 includes a semiconductor substrate 12, an upper electrode 14, and a lower electrode 16. The semiconductor substrate 12 is a silicon substrate. The upper electrode 14 is formed on a top surface of the semiconductor substrate 12. The lower electrode 16 is formed on a bottom surface of the semiconductor substrate 12. The semiconductor substrate 12 includes an IGBT region 90 in which an IGBT is formed and a diode region 92 in which a diode is formed.

(11) In the semiconductor substrate 12 in the IGBT region 90, an emitter region 20, a body region 22, a pillar region 24, a barrier region 26, a drift region 28, a buffer region 30, and a collector region 32 are formed.

(12) The emitter region 20 has an n-type impurity and is formed in a range exposed on the top surface of the semiconductor substrate 12. The emitter region 20 forms an ohmic contact with the upper electrode 14.

(13) The body region 22 has a p-type impurity and is formed In the range exposed on the top surface of the semiconductor substrate 12. The body region 22 includes a body contact region 22a and a low concentration body region 22b. The body contact region 22a is formed in the range exposed on the top surface of the semiconductor substrate 12. The body contact region 22a has a high p-type impurity concentration and forms an ohmic contact with the upper electrode 14. The low concentration body region 22b is formed on the lower side of the emitter region 20 and the body contact region 22a and on the lateral side of the body contact region 22a. A p-type impurity concentration in the low concentration body region 22b is lower than that in the body contact region 22a.

(14) The pillar region 24 has an n-type impurity and is formed in the range exposed on the top surface of the semiconductor substrate 12. The pillar region 24 is in contact with the low concentration body region 22b on the lateral side of, the low concentration body region 22b. The pillar region 24 extends along a depth from the top surface of the semiconductor substrate 12 to a lower end of the body region 22. In other words, an n-type region that contacts with the body region 22 from the lateral side in a position shallower than the lower end of the body region 22 is the pillar region 24. The pillar region 24 is separated from the emitter region 20 by the body region 22. An n-type impurity concentration in the pillar region 24 is lower than that in the emitter region 20 and higher than that in the drift region 28. The pillar region 24 has the n-type impurity concentration of 110.sup.15 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3 at a position exposed on the top surface of the semiconductor substrate 12 (that is, a position that contacts with the upper electrode 14). Therefore, the pillar region 24 forms a Schottky connection with the upper electrode 14.

(15) The barrier region 26 has an n-type impurity and is formed on the lower side of the body region 22 and the pillar region 24. The barrier region 26 is separated from the emitter region 20 by the body region 22. An n-type impurity concentration in the barrier region 26 is lower than that in the emitter region 20 and higher than that in the drift region 28. The barrier region 26 preferably has the n-type impurity concentration of 110.sup.15 atoms/cm.sup.3 or more and less than 110.sup.18 atoms/cm.sup.3.

(16) The drift region 28 has an n-type impurity and is formed on the lower side of the barrier region 26. The drift region 28 is separated from the body region 22 by the barrier region 26. In the drift region 28, an n-type impurity concentration is substantially uniformly distributed. In other words, a region in which the n-type impurity concentration is substantially uniformly distributed is the drift region 28, and a region that is present on the upper side of the drift region 28 and in which the n-type impurity concentration is larger than a value of n-type impurity concentration substantially uniformly distributed is the barrier region 26.

(17) The buffer region 30 has an n-type impurity and is formed on the lower side of the drift region 28. An n-type impurity concentration in the buffer region 30 is larger than that in the drift region 28.

(18) The collector region 32 has a p-type impurity and is formed on the lower side of the buffer region 30. The collector region 32 is formed in the range exposed on the lower surface of the semiconductor substrate 12. The collector region 32 forms an ohmic connection with the lower electrode 16.

(19) On the top surface of the semiconductor substrate 12 in the IGBT region 90, a plurality of trenches is formed. Each of the trenches penetrates through the emitter region 20, the low concentration body region 22b and the barrier region 26 and reaches the drift region 28. An inner surface of each of the trenches is covered with a gate insulating film 40. In each of the trenches, a gate electrode 42 is formed. The gate electrode 42 is insulated from the semiconductor substrate 12 by the gate insulating film 40. The gate electrode 42 faces the emitter region 20, the low concentration body region 22b, the barrier region 26 and the drift region 28 via the gate insulating film 40. A top surface of the gate electrode 42 is covered with an insulating film 44. The gate electrode 42 is insulated from the upper electrode 14 by the insulating film 44.

(20) In the semiconductor substrate 12 in the diode region 92, an anode region 34, the pillar region 24, the barrier region 26, the drift region 28, the buffer region 30 and a cathode region 36 are formed.

(21) The anode region 34 has a p-type impurity and is formed in the range exposed on the top surface of the semiconductor substrate 12. The anode region 34 includes an anode contact region 34a and a low concentration anode region 34b. The anode contact region 34a is formed in the range exposed on the top surface of the semiconductor substrate 12. The anode contact region 34a has a high p-type impurity concentration and forms an ohmic contact with the upper electrode 14. The low concentration anode region 34b is formed on the lower side and on the lateral side of the anode contact region 34a. A p-type impurity concentration in the low concentration anode region 34b is lower than that in the anode contact region 34a. The anode region 34 is formed in the range of a depth substantially the same as that of the body region 22,

(22) On the lateral side of the low concentration anode region 34b, the above-described pillar region 24 is formed.

(23) On the lower side of the low concentration anode region 34b and the pillar region 24 in the diode region 92, the above-described barrier region 26 is formed.

(24) On the lower side of the barrier region 26 in the diode region 92, the above-described drift region 28 is formed. The drift region 28 continuously extends from the IGBT region 90 to the diode region 92.

(25) On the lower side of the drift region 28 in the diode region 92, the above-described buffer region 30 is formed. The buffer region 30 continuously extends from the IGBT region 90 to the diode region 92.

(26) On the lower side of the buffer region 30 in the diode region 92, the cathode region 36 is formed. The cathode region 36 has an n-type impurity and has the n-type impurity concentration higher than that in the buffer region 30. The cathode region 36 is formed in the range exposed on the bottom surface of the semiconductor substrate 12. The cathode region 36 forms an ohmic contact with the lower electrode 16.

(27) On the top surface of the semiconductor substrate 12 in the diode region 92, a plurality of trenches is formed. Each of trenches penetrates through the anode region 34 and the barrier region 26 and reaches the drift region 28. An inner surface of each of the trenches is covered with an insulating film 50. A control electrode 52 is formed in each of the trenches. The control electrode 52 is insulated from the semiconductor substrate 12 by the insulating film 50. A top surface of the control electrode 52 is covered with an insulating film 54. The control electrode 52 is insulated from the upper electrode 14 by the insulating film 54.

(28) In the IGBT region 90 and the diode region 92, a Schottky diode is formed by the upper electrode 14 and the pillar region 24 that forms, a Schottky connection with the upper electrode 14. When a voltage by which the upper electrode 14 becomes a positive side with respect to the lower electrode 16 (hereinafter, referred to as a diode forward voltage) is input to the semiconductor device 10, the Schottky diode is turned on. That is, as shown by arrow marks 60 of FIG. 1, a current flows from the upper electrode 14 to the lower electrode 16 via the pillar region 24, the barrier region 26, the drift region 28, the buffer region 30 and the cathode region 36. Further, in the diode region 92, a pn-junction is formed from the anode region 34 and the barrier region 26. Further, in the IGBT region 90, a pn-junction is formed from the body region 22 and the barrier region 26. However, in a state where the above-described diode forward voltage is applied, these pn-junctions are difficult to be turned on, and holes are suppressed from being supplied to the drift region 28. That is, since the barrier region 26 has substantially the same potential as the pillar region 24 and the pillar region 24 forms a Schottky connection with the upper electrode 14, a potential difference between the barrier region 26 and the upper electrode 14 becomes substantially the same as a voltage drop in a Schottky interface. The voltage drop is sufficiently smaller than a built-in voltage of the above-described pn diode. Thus, the pn-junction becomes difficult to be turned on. Therefore, the holes that flow in the drift region 28 from the anode region 34 and the body region 22 are very scarce.

(29) When a voltage applied to the semiconductor device 10 is switched from the diode forward voltage to a reversed direction thereof (a voltage by which the lower electrode 16 becomes a positive side with respect to the upper electrode 14), the diode performs a reverse recovery operation. That is, the holes present in the drift region 28 are discharged to the upper electrode 14 via the anode region 34 and the body region 22. Thus, a reverse current instantaneously flows to the diode. However, in the semiconductor device 10, as described above, in a state in which the diode forward voltage is applied, the holes supplied to the drift region 28 are scarce. Therefore, at a time when the applied voltage is switched to a reverse direction, the holes present in the drift region 28 are scarce. Therefore, at a time when the applied voltage is switched to the reverse direction, the holes that are discharged to the upper electrode 14 are scarce. Thus, in the semiconductor device 10, the current is difficult to flow during the reverse recovery operation of the diode, and the switching loss is small.

(30) In a state in which a voltage that makes the lower electrode 16 positive with respect to the upper electrode 14 is applied to the semiconductor device 10; when a high potential (a potential higher than a gate-on potential) is applied to the gate electrode 42, the IGBT is turned on because a channel is formed in the body region 22.

(31) In a state in which a voltage that makes the lower electrode 16 positive with respect to the upper electrode 14 is applied to the semiconductor device 10, when a low potential (a potential lower than the gate-on potential) is applied to the gate electrode 42, the IGBT is turned off because a channel is not formed in the body region 22. In this case, a depletion layer expands from a pn-junction at a boundary between the body region 22 and the bather region 26 into the drift region 28. Further, the depletion layer slightly expands from the pn-junction also into the body region 22. At this time, when the n-type impurity concentration is high in the bather region 26, the depletion layer is likely to expand into the body region 22, and resistance of the body region 22 becomes high. In the case where the resistance of the body region 22 is high, when the IGBT is turned on, the potential of the body region 22 is likely to be high. Therefore, a current is likely to flow from the body region 22 that is not channeled to the emitter region 20. Thus, when the current flows from the body region 22 that is not channeled to the emitter region 20, a parasitic npn transistor constituted by the emitter region 20, the body region 22 and the barrier region 26 is turned on. Since a current of the parasitic npn transistor becomes a base current of a parasitic pnp transistor constituted with the body region 22, the n-type regions 26 to 30 and the collector region 32, the parasitic pnp transistor is also turned on. As a result, a parasitic thyristor constituted by the parasitic npn-transistor and the parasitic pnp-transistor is turned on, and a current control becomes difficult. That is, in the IGBT region 90, so-called latch-up is generated. However, according to the semiconductor device 10 of Embodiment 1, as described below, the n-type impurity concentration in the barrier region 26 is low. Thus, the latch-up is difficult to occur.

(32) FIG. 2 shows impurity concentration distributions along a II-II line of FIG. 1. In each of graphs that show impurity concentrations disclosed in the drawings, a vertical axis shows a depth (position) from the top surface of the semiconductor substrate 12, and a horizontal axis shows an impurity concentration in a logarithmic scale. As shown in FIG. 2, the n-type impurity concentration rises as proceeds from the top surface (a position at an upper end of FIG. 2) of the semiconductor substrate 12 to a deeper position and takes a maximum value A1 in the pillar region 24. On the lower side than the depth of the maximum value A1, the n-type impurity concentration decreases as proceeds to a deeper position while forming a mild curve. Then, in the proximity of the boundary of the pillar region 24 and the barrier region 26, a folding point X1 in which a slope of the n-type impurity concentration discontinuously changes is formed. On the lower side than the folding point X1, the n-type impurity concentration decreases as proceeds to a deeper position while forming a mild curve. In the drift region 28, the n-type impurity concentration is distributed with a low and substantially constant concentration. Further, as shown in FIG. 2, in the pillar region 24, the p-type impurity is distributed at a relatively high concentration.

(33) Each of the semiconductor layers on the top surface side of the semiconductor device 10 is formed by impurity implantation and by impurity diffusion. Since a method of manufacturing the semiconductor device 10 of Embodiment 1 has features in the steps of forming the pillar region 24, the barrier region 26 and the low concentration body region 22b, these steps will be described below.

(34) Before execution of a step of implanting an impurity, the n-type impurity in the semiconductor substrate 12 has, as shown in a graph n1 of FIG. 3, a substantially uniform distribution over an entirety in the semiconductor substrate 12. The n-type impurity concentration (a concentration of graph n1) at this time is substantially the same as the n-type impurity concentration in the drift region 28 shown in FIG. 2.

(35) In a step of forming the low concentration body region 22b, of the top surface of the semiconductor substrate 12, over a nearly entire region of the IGBT region 90 and the diode region 92, a p-type impurity is implanted, after that, the implanted p-type impurity is diffused. Thus, the low concentration body region 22b is formed. At this time, also the low concentration anode region 34b is simultaneously formed. Thus, since over a nearly entire region of the IGBT region 90 and the diode region 92, the p-type impurity is implanted, as shown in FIG. 3, the p-type impurity is implanted also in a region where the pillar region 24 is to be formed.

(36) In a step of forming the barrier region 26, of the top surface of the semiconductor substrate 12, the n-type impurity is implanted over a nearly entire region of the IGBT region 90 and the diode region 92. Here, in the proximity (a very shallow position) of the top surface of the semiconductor substrate 12, the n-type impurity is implanted. Thereafter, the implanted n-type impurity is diffused. Here, a time, conditions and the like of the diffusion step are adjusted such that a diffusion distance of the n-type impurity becomes longer. Thus, as shown in a graph n2 of FIG. 3, the n-type impurity can be broadly distributed to a deep position.

(37) In a step of forming the pillar region 24, a mask in which an opening is formed in a range corresponding to the pillar region 24 is formed on the semiconductor substrate 12. Then, the n-type impurity is implanted in the semiconductor substrate 12 through the mask. Thus, the n-type impurity is implanted only in a region in which the pillar region 24 is to be formed. Further, here, an implanting energy of the n-type impurity is controlled such that the average stop position of the n-type impurity that is implanted in the semiconductor substrate 12 may be a depth of the maximum value A1 of FIGS. 2 and 3 (that is, such that the maximum value A1 may be located in the pillar region 24). When the n-type impurity is implanted, the implanted n-type impurity is diffused, and the n-type impurity is distributed as shown in a graph n3 of FIG. 3.

(38) The step of forming the low concentration body region 22b, the step of forming the barrier region 26 and the step of forming the pillar region 24, which are described above may be performed in any order.

(39) When the impurity is implanted and diffused as described above, as shown in FIG. 2, the impurity concentration distribution that has the maximum value A1 and the folding point X1 can be obtained. The graph n2 of FIG. 3 broadly extends to a side lower than the graph n3. Thus, by a part where the graph n2 expands to a lower side than the graph n3, the barrier region 26 is formed.

(40) . According to the method described above, on a lower side than a region (a region of the graph n3 of FIG. 3) in which the n-type impurity that is implanted in the pillar region 24 is distributed, the n-type impurity that is implanted in the barrier region 26 is distributed (the graph n2 of FIG. 3). In other words, the n-type impurity, that is implanted in the step of forming the pillar region 24 is not so much distributed in the barrier region 26. Therefore, the n-type impurity concentration in the barrier region 26 is low. Therefore, the semiconductor device 10 is unlikely to cause the latch-up.

(41) Across-sectional structure of a semiconductor device of Embodiment 2 is the same as that of the semiconductor device 10 of Embodiment 1 shown in FIG. 1. In the semiconductor device of Embodiment 2, when viewed along a II-II line of FIG. 1, the impurities are distributed as shown in FIG. 4. In the semiconductor device of Embodiment 2, in the same manner as the semiconductor device 10 of Embodiment 1, the n-type impurity concentration has the maximum value A1. Further, on the lower side of the folding point X1 that is formed on the lower side of the maximum value A1, the n-type impurity concentration changes to an increase. That is, at the folding point X1, the n-type impurity concentration has a minimum value. Further, on the lower side of the folding point X1, a maximum value A2 of the n-type impurity concentration is formed. The maximum value A2 is present within the barrier region 26. On the lower side of the maximum value A2, the n-type impurity concentration decreases to a concentration in the drift region 28. Further, a p-type impurity concentration distribution of FIG. 4 is substantially the same as the p-type impurity concentration distribution of FIG. 2.

(42) According to the method of manufacturing the semiconductor device of Embodiment 2, the step of forming the low concentration body region 22b and the step of forming the pillar region 24 are performed in substantially the same manner as Embodiment 1. Therefore, distributions shown in graphs n1, n3 and p of FIG. 5 are obtained. According to the method of manufacturing of Embodiment 2, the step of forming the barrier region 26 is performed such that the average stop position of the n-type impurity becomes a depth corresponding to the barrier region 26. Thereafter, the step of diffusing the implanted n-type impurity is performed such that the diffusion distance becomes relatively short. Therefore, the implanted n-type impurity is distributed as shown in the graph n2 of FIG. 5. That is, in the barrier region 26, the maximum value A2 is formed. In the method, as shown in. FIG. 5, in a region having a relatively low n-type impurity concentration in the graph n3 (that is, a side deeper than the maximum value A1), the barrier region 26 is formed. Therefore, the barrier region 26 can be formed by implanting the n-type impurity of relatively low concentration. Thus, the n-type impurity concentration in the barrier region 26 can be reduced. Therefore, the semiconductor device of Embodiment 2 is unlikely to cause the latch-up.

(43) A cross-sectional structure of a semiconductor device of Embodiment 3 is the same as that of the semiconductor device 10 of Embodiment 1 shown in FIG. 1. In the semiconductor device of Embodiment 3, when viewed along a II-II line of FIG. 1, the impurity is distributed as shown in FIG. 6. In the semiconductor device of Embodiment 3, in the same manner as the semiconductor device 10 of Embodiment 2, the n-type impurity concentration has the maximum values A1 and A2 and the folding point X1.

(44) According to the method of manufacturing the semiconductor device of Embodiment 3, the step of forming the low concentration body region 22b and the step of forming the pillar region 24 are performed in substantially the same manner as those of Embodiment 1. Therefore, distributions shown in the graphs n1, n3 and p of FIG. 7 are obtained. According to the method of manufacturing of Embodiment 2, the step of forming the barrier region 26 is performed such that the average stop position of the n-type impurity becomes a depth corresponding to the barrier region 26. Further, the n-type impurity is implanted such that the average stop position becomes a depth in which the n-type impurity that is implanted by the impurity implantation in the pillar region 24 is not distributed. Therefore, as shown in FIG. 7, the maximum value A2 is formed at a depth in which a value of the graph n3 is substantially zero. Thus, by forming the barrier region 26 at a depth in which the value of the graph n3 is substantially zero, the n-type impurity concentration in the barrier region 26 can be more reduced. Therefore, the semiconductor device of Embodiment 3 is unlikely to cause the latch-up.

(45) In a semiconductor device of Embodiment 4, as shown in FIG. 8, a lower body region 80 is formed between the bather region 26 and the drift region 28. Other structures of the semiconductor device of Embodiment 4 are the same as those of the semiconductor device of Embodiment 1.

(46) In the semiconductor device of Embodiment 1, when the IGBT is being turned off, the barrier region 26 and the drift region 28 are depleted, and a voltage is held by the depleted regions. Since a corner part 22c of the body region 22 (a corner part that faces the pillar region 24 and the barrier region 26: see FIG. 1) faces the depleted regions like this, an electric field is likely to be concentrated at the corner part 22c.

(47) On the other hand, in the semiconductor device of Embodiment 4, a depletion layer expands mainly from the lower body region 80 into the drift region 28. Therefore, a voltage is applied mainly to, the drift region 28. Therefore, it is neither likely that a high voltage is generated in the proximity of the corner part 22c of the body region 22 nor likely that the electric field is concentrated at the corner part 22c. Therefore, the semiconductor device of Embodiment 4 has high avalanche resistance.

(48) Further, when the lower body region 80 is formed by implantation and diffusion of the impurity, a part of a p-type impurity that is implanted in the lower body region 80 is distributed also to the barrier region 26. Since the p-type impurity becomes a counterpart of the n-type impurity in the barrier region 26, an essential n-type impurity concentration in the barrier region 26 becomes low. Therefore, the depletion layer becomes more difficult to be expanded into the body region 22. Therefore, the semiconductor device of Embodiment 4 is more unlikely to cause the latch-up.

(49) In each of the Embodiments described above, in the step of implanting the p-type impurity in the low concentration body region 22b, the p-type impurity was implanted- also in the pillar region 24. However, in the relevant step, a surface corresponding to the pillar region 24 may be masked so as not to implant the p-type impurity in the pillar region 24. According to such a structure, an implantation concentration of the n-type impurity in the step of forming the pillar region 24 can be reduced. As a result, also the implantation concentration of the n-type impurity in the step of forming the barrier region 26 can be reduced. Therefore, the semiconductor device can be more unlikely, to cause the latch-up. In this case, an average value of the p-type impurity concentration in the pillar region 24 can be set to less than 110.sup.15 atoms/cm.sup.1.

(50) Further, in each of the Embodiments described above, although the anode region 34 was formed in the diode region 92, the anode region 34 is not necessarily needed. For example, on an entire top surface side of the semiconductor substrate 12, a structure of a top surface side of the IGBT region 90 of FIG. 1 may be formed. The body region 22 in the IGBT region 90 can operate in substantially the same manner as the anode region 34. Further, as described above, the pillar region 24 in the IGBT region 90 operates in substantially the same manner as the pillar region 24 in the diode region 92. In this case, the body region 22 combines a function as the anode region 34. Therefore, even in such a structure, in substantially the same manner as each of the Embodiments described above, the semiconductor device can be operated.

(51) Further, in each of the Embodiments described above, although the buffer region 30 was formed, the buffer region 30 may not be formed. That is, the drift region 28 may come into direct contact with the collector. region 32.

(52) Further, in each of the Embodiments described above, although the folding point X1 is located in the bather region 26, the folding point X1 may be located in the pillar region 24.

(53) While specific Embodiments of the present invention have been described in detail, these are only illustrations and do not limit the present invention. Various changes and modifications of the specific Embodiments exemplified in the above) are included in the present invention. Technical elements described in the present specification or drawings exert technical usefulness singularly or in various combinations thereof.