A solid-state imaging device and an electronic apparatus are to be provided to solve problems in processing in a structure in which an active chip is bonded to the wafer of a solid-state imaging element chip and is covered with an insulating film such as an oxide film.

The solid-state imaging device includes: a solid-state imaging element chip; an active chip bonded to the lower surface of the solid-state imaging element chip; a dummy chip that is bonded to the lower surface of an electrode pad of the solid-state imaging element chip and has an end surface parallel to the cutting plane of the solid-state imaging element chip cut out from a wafer; and a planarized insulating film that covers the bonding surface, or a solid-state imaging element chip; an active chip bonded to the solid-state imaging element chip; one or more dummy chips that are bonded to a free region on the bonding surface; and a planarized insulating film that covers the bonding surface side, or a solid-state imaging element chip; an active chip bonded to the solid-state imaging element chip; a planarized insulating film that covers the peripheral side surfaces and the lower surface of the active chip; and a silicon substrate that surrounds the peripheral side surfaces of the insulating film and has a lower surface formed in the same plane as the insulating film.

Provided are a photoelectric conversion element and a photoelectric conversion device that are thin, have high conversion efficiency, and allow device scale-up. The photoelectric conversion element includes a photoelectric conversion member containing a transition metal dichalcogenide, and a first electrode and a second electrode that are connected to the photoelectric conversion member, in which the first electrode and the second electrode include facing portions where at least a part of the first electrode and at least a part of the second electrode are arranged to face each other in a parallel manner, and a length W of each of the facing portions and a separation distance Lch between the first electrode and the second electrode at the facing portions satisfy a relationship of W/Lch36.7. The photoelectric conversion device includes the photoelectric conversion element.

In one aspect, a preparation method for a solar cell includes: providing a silicon wafer substrate having a first surface and a second surface opposite to the first surface; forming a silicon-containing film on the first surface of the silicon wafer substrate; patterning the silicon-containing film on the first surface by laser to form a patterned region; placing the silicon wafer substrate having the silicon-containing film and the patterned region into an alkaline solution containing a strong monobasic base to obtain a pre-treated silicon wafer substrate, and placing the pre-treated silicon wafer substrate into a texturing liquid containing a strong monobasic base for texturing treatment, wherein a concentration of the strong monobasic base in the alkaline solution is greater than a concentration of the strong monobasic base in the texturing liquid.

Implementations relating to a back contact solar cell and its preparation method are provided in this disclosure. In an implementation, a back contact solar cell includes a silicon substrate having a first surface. The first surface comprises a first conductive region, a second conductive region, and an insulation region located between the first conductive region and the second conductive region. The back contact solar cell further comprises a first transport layer located on the first conductive region and a second transport layer located on the second conductive region. The second transport layer extends from the second conductive region through the insulation region to the first conductive region, and partially covers the first transport layer, wherein a thickness of a first portion of the second transport layer located on the insulation region is greater than a thickness of a second portion of the second transport layer located on the second conductive region.

A disclosed semiconductor photodetector includes a first semiconductor layer having a first refractive index and a first band gap; a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a second refractive index and a second band gap; a first electrode; and a second electrode. The second refractive index is greater than the first refractive index, and the second band gap is smaller than the first band gap. The first semiconductor layer includes a p-type first region, an n-type second region, and a non-conductive third region between the first region and the second region. The second semiconductor layer includes a p-type fourth region in ohmic contact with the first electrode, an n-type fifth region in ohmic contact with the second electrode, and a non-conductive sixth region between the fourth region and the fifth region.

The present disclosure provides back-contact solar cells, and methods for manufacturing back-contact solar cells. In one aspect, a back-contact cell comprising a silicon substrate, a first doped semiconductor layer on a back surface of the silicon substrate in first regions, and a second doped semiconductor layer on the back surface of the silicon substrate in second regions. The first regions and the second regions are alternately distributed at intervals. The back surface of the silicon substrate comprises an isolation region between a first region and a second region adjacent to the first region. A surface of the isolation region is recessed into the silicon substrate. A depth by which the surface of the isolation region is recessed into the silicon substrate relative to the surface of the at least one of the first regions is less than 3000 nm.

Disclosed are a solar cell and a photovoltaic module. The solar cell includes a substrate and a doped semiconductor layer disposed on the substrate. The solar cell further includes holes distributed across an edge region of the doped semiconductor layer, and a respective hole of the holes extending through at least the doped semiconductor layer and being filled with a passivation material. The solar cell further includes a passivation layer formed on a side of the doped semiconductor layer away from the substrate, and a plurality of electrodes arranged at intervals along a first direction, extending through the passivation layer and in electrical contact with the doped semiconductor layer.

An electrical connection is formed between first and second conductive elements, by inserting a nano-metal material between the first and second conductive elements; and heating the nano-metal material to a melting temperature to form the electrical connection between the first and second conductive elements. The nano-metal material may comprise a nano-metal paste or ink comprised of one or more of Gold (Au), Copper (Cu), Silver (Ag), and/or Aluminum (Al) nano-particles that melt or fuse into a solid to form the electrical connection, at a melting temperature of about 150-250 degrees C., and more preferably, about 175-225 degrees C. The electrical connection may be formed between a solar cell and a substrate by creating a via in the solar cell between a front and back side of the solar cell, wherein the via is connected to a contact on the front side of the solar cell and a trace on the substrate.

Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The pad includes a side edge and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The structure further comprises a second waveguide core including a section adjoined to the side edge of the pad adjacent to the first waveguide core.

A method of manufacturing an infrared device is provided. The method includes: a step of forming a first semiconductor layer of first conductive type on one face side of a substrate; a step of forming a second semiconductor layer serving as an active layer on the first semiconductor layer; a step of forming a third semiconductor layer of second conductive type on the second semiconductor layer; a first etching step of forming a first mesa portion including an upper side portion of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer by applying a dry etching process with an interelectrode voltage 330V or higher; and a second etching step of applying a dry etching process with an interelectrode voltage less than 330V.