The present disclosure relates to a solar cell, a preparation method thereof, and a photovoltaic module. The solar cell includes a semiconductor substrate, passivating contact structures, a dielectric layer, and first electrodes. The semiconductor substrate includes a first surface and a second surface opposite to each other. The semiconductor substrate includes passivation regions and passivated contact regions, which are alternately arranged along a first direction. The first direction is perpendicular to a thickness direction of the semiconductor substrate. The passivating contact structures are disposed on the second surface and correspondingly disposed on the passivated contact regions. Each passivating contact structure includes an electrically conductive passivation layer. The dielectric layer at least covers the second surface in the passivation regions. The first electrodes are disposed on the passivating contact structures at a side away from the semiconductor substrate. Each passivating contact structure is provided with at least one first electrode.

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

The present invention relates to an emitter wrap-through solar cell and a method for preparing the same. The solar cell according to the present invention has a structure that may minimize generation of leakage current and minimize energy conversion efficiency measurement error. And, the preparation method of a solar cell according to the present invention may easily confirm the alignment state of the electrode, and thus, provide more improved productivity.

A solar cell using a printed circuit board (PCB) includes a substrate that is formed of an insulating material and in and through which a plurality of fixing holes and communication holes are alternately formed; a plurality of photoelectric effect generators that have ball or polyhedral shapes fixed to the substrate to be disposed over the plurality of fixing holes, and generate photoelectric effects by receiving light through light-receiving portions that are exposed to an upper portion of the substrate; a plurality of upper electrodes that are formed on a top surface of the substrate, and are connected to the respective light-receiving portions of the photoelectric effect generators; and a plurality of lower electrodes that are formed on a bottom surface of the substrate to be connected to respective non-light-receiving portions of the photoelectric effect generators, and communicate with the plurality of upper electrodes through the plurality of communication holes.

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

The invention relates to a method for texturing a semiconductor substrate (1), comprising steps consisting in forming a plurality of cavities of random shapes, depths and distribution, in an etch mask (2), by means of non-homogeneous reactive-ion etching, forming a first rough random design, and etching the substrate using the etch mask, by means of reactive-ion etching, in such a way as to transfer the first rough random design into the substrate and to produce a second rough random design (200), comprising cavities (20) of random shapes, depths (d2r) and distribution, on the surface of the substrate.

The present disclosure relates to a solid-state imaging device capable of further decreasing reflectivity, a method of manufacturing the same, and an electronic device.

The solid-state imaging device includes a semiconductor substrate on which a photoelectric converting unit is formed for each of a plurality of pixels, and an antireflection structure provided on a light incident surface side from which light is incident on the semiconductor substrate in which a plurality of types of projections of different heights is formed. The antireflection structure is formed by performing processing of digging a light incident surface of the semiconductor substrate in a plurality of stages with different processing conditions. The antireflection structure is the structure in which a second projection lower than a first projection is formed between the first projections of predetermined height. The present technology may be applied to a CMOS image sensor, for example.

Methods for forming passivated contacts include implanting compound-forming ions into a substrate to about a first depth below a surface of the substrate, and implanting dopant ions into the substrate to about a second depth below the surface. The second depth may be shallower than the first depth. The methods also include annealing the substrate.