A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

A capacitor-less semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a first metal-oxide semiconductor film, a second metal-oxide semiconductor film spaced apart from the first metal-oxide semiconductor film, a first gate electrode intersecting the first metal-oxide semiconductor film and the second metal-oxide semiconductor film, a first gate dielectric film interposed between the first metal-oxide semiconductor film and the first gate electrode, a charge storage film in the first gate dielectric film, the charge storage film extending along at least a portion of the first metal-oxide semiconductor film and connected to the second metal-oxide semiconductor film, a second gate electrode spaced apart from the first gate electrode and intersecting the second metal-oxide semiconductor film, and a second gate dielectric film interposed between the second metal-oxide semiconductor film and the second gate electrode.

According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.

Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.

A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.

To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.

There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.