A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 110.sup.19 cm.sup.3 to about 1010.sup.19 cm.sup.3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.

A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.