Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a control gate electrode and a memory gate electrode, a conductive film on an insulating film made of a high-dielectric-constant film via a metal film; patterning the conductive film and thereby forming a gate electrode including the metal film and the conductive film in a high-voltage MISFET region, while forming a metal film portion and a conductive film portion in a low-voltage MISFET region; and then, removing the conductive film portion from the low-voltage MISFET region, forming another conductive film on the metal film portion, and forming a gate electrode including the metal film portion and the another conductive film.

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.

There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a conductor and a sidewall insulating film. The sidewall insulating film is provided between the conductor and the insulator and between the conductor and the electrode layers. The conductor contacts the major surface of the substrate. The blocking insulating film is provided between the sidewall insulating film and the insulator, between the insulator and the electrode layers, and between the charge storage film and the electrode layers. The blocking insulating film includes a first blocking insulating layer and a second blocking insulating layer, the second blocking insulating layer being different from the first blocking insulating layer.

An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.