High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.

A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

The present invention discloses a dual-well complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The dual-well CMOS device includes a PMOS device region and an NMOS device region. Each of the PMOS and NMOS device regions includes a dual-well (which includes a P-well and an N-well), and each of the PMOS and NMOS device regions includes P-type and N-type lightly doped diffusions (PLDD and NLDD) regions respectively in different wells in the dual well. A separation region is located between the PMOS device region and the NMOS device region, for separating the PMOS device region and the NMOS device region. The depth of the separation region is not less than the depth of any of the P-wells and the N-wells in the PMOS device region and the NMOS device region.

Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

An integrated circuit includes a doping region extending in a first direction, the doping region being doped with a first-type dopant; a gate structure at least partially overlapping the doping region; a drain contact region in the doping region and spaced apart from the gate structure in the first direction, the drain contact region being doped with the first-type dopant at a higher concentration than the doping region; a dielectric layer on the doping region between the gate structure and the drain contact region; a first contact electrically connected to the dielectric layer; and a second contact electrically connected to the drain contact region and electrically connected to the first contact.

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over a high-voltage N-type well region, an N-type well region and a P-type well region. The gate oxide layer includes a first layer portion and a second layer portion. The first and second layer portions have different thicknesses. A main gate is formed on the first layer portion and the second layer portion. At least one split gate is formed on the second layer portion, and the main gate and the split gate extend along an interface between the high-voltage N-type well region and the P-type well region. An inter-level dielectric (ILD) layer is formed over the main gate and the split gate. A plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate are formed. An electrode is formed to contact the connecting features.

A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.