The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N, a second nitride region including Al.sub.x2Ga.sub.1-x2N, and a third nitride region including Al.sub.x3Ga.sub.1-x3N. The second nitride region is provided between the first and third nitride regions in a first direction from the first nitride region to the second nitride region. The second nitride region includes carbon and oxygen. The first nitride region does not include carbon, or a second carbon concentration in the second nitride region is higher than a first carbon concentration in the first nitride region. The second carbon concentration is higher than a third carbon concentration in the third nitride region. A ratio of a second oxygen concentration in the second nitride region to the second carbon concentration is not less than 1.010.sup.4 and not more than 1.410.sup.3.

The present disclosure provides a fabricating method of a high electron mobility transistor device, including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

Provided are a nitride semiconductor buffer structure and a semiconductor device including the same. The buffer structure may include a plurality of buffer layers between a substrate and an active layer. The active layer may include a nitride semiconductor. The plurality of buffer layers may be stacked on each other on the substrate. Each of the plurality of buffer layers may have a super lattice structure and may include a doped nitride semiconductor. The plurality of buffer layers may have different compositions from each other. Adjacent buffer layers, among the plurality of buffer layers, may have different doping concentrations from each other.

Disclosed are a semiconductor structure and a method for preparing the same, relating to the field of semiconductor technologies. The semiconductor structure includes: a substrate; and a plurality of functional film layers stacked on the substrate, the plurality of functional film layers include a first semiconductor layer and a second semiconductor layer stacked with each other, the first semiconductor layer is arranged between the substrate and the second semiconductor layer. The first semiconductor layer includes a plurality of defect pits recessed toward the substrate, the defect pits are filled by the second semiconductor layer, and one side of the second semiconductor layer away from the first semiconductor layer is a plane. The semiconductor structure and the preparation method thereof provided in the present application solve the problem of vertical leakage in the semiconductor structure in the prior art.

The embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing thereof, the semiconductor structure includes a substrate and a channel structure at a side of the substrate, and the channel structure includes a first channel layer and a first barrier layer which are sequentially disposed at a side of the substrate; where the semiconductor structure includes a gate region, and a source region and a drain region at both sides of the gate region, the channel structure in the source region is provided with a first groove, and the channel structure in the drain region is provided with a second groove; and two N-type heavily doped layers are in the first groove and the second groove respectively, where a surface of the N-type heavily doped layers away from the substrate has a plurality of V-shaped pits.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A trench field effect transistor (TFET) may include a semiconductor layer having a trench therein, and a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The TFET may further include source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.