A method for making a trench field effect transistor (TFET) may include forming a trench in a semiconductor layer, and forming a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench, the superlattice layer comprising a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and forming a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.

A transistor having normally-off characteristics included in the nitride semiconductor device includes a gate insulating film provided on a first surface side of the nitride semiconductor substrate, a gate electrode provided on the gate insulating film, a p-type layer located to be opposed to the gate electrode with the gate insulating film interposed, and an n-type layer located to be opposed to the gate electrode with the p-type layer interposed so as to be in contact with the p-type layer. A Mg concentration in the p-type layer is 110.sup.18 cm.sup.3 or higher and 110.sup.20 cm.sup.3 or lower. The inequalities (1) and (2) are fulfilled, where an effective acceptor concentration of the p-type layer is Np (cm.sup.3), a thickness of the p-type layer is dp (nm), an effective donor concentration of the n-type layer is Nn (cm.sup.3), and a thickness of the n-type layer is dn (nm).

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed above the second nitride semiconductor layer. The first nitride semiconductor layer is a layer including GaN. An X-ray rocking curve for a surface of the first nitride semiconductor layer has a half width that is 1100 arcseconds greater and 1400 arcseconds or less.

The disclosure provides a structure base portions having different germanium concentrations, and related methods. A structure of the disclosure includes a base region including a first portion on a first emitter/collector (E/C) terminal and including germanium (Ge). A Ge concentration in the first portion varies with respect to distance from the first E/C terminal. A second portion is on the first portion and includes Ge. A third portion is between the second portion and a second E/C terminal and includes Ge. A Ge concentration in the third portion varies with respect to distance between the second portion and the second E/C terminal.

A semiconductor structure includes a substrate, a nucleation layer, a superlattice layer, a first graded layer, a second graded layer, a breakdown voltage layer, a channel layer, and a barrier layer. The nucleation layer is disposed between the substrate and the superlattice layer. The superlattice layer is formed by alternating a high-aluminum layer and a low-aluminum layer, with an average aluminum composition ranging from 70% to 90%. The first graded layer has an average aluminum composition ranging from 40% to 70%. The second graded layer is disposed on the first graded layer and has an average aluminum composition ranging from 30% to 40%. The channel layer is disposed between the breakdown voltage layer and the barrier layer. The total thickness from the nucleation layer to the barrier layer ranges from 700 nm to 3000 nm.