In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.

A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a silicon substrate and depositing a photoresist material there-over, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a silicon face having a in orientation, and forming a 2DEG on at least one sidewall.

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 110.sup.15 cm.sup.3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.

The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a Vertical Cylindrical GaN Quantum Well Power Transistor for high power application is disclosed. Compared with the prior art, the method of forming a quantum well device disclosed in the present invention has the beneficial effects of high mobility and high breakdown voltage with better performance and reliability.

Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.

A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.

A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.