A nitride semiconductor device includes: a substrate; a drift layer, a high-resistance layer, and a first base layer above the substrate in stated order; a gate opening penetrating through the first base layer and the high-resistance layer to the drift layer; an electron transport layer and an electron supply layer covering an upper portion of the first base layer and the gate opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; an electrode opening penetrating through the electron supply layer and the electron transport layer to the first base layer; a potential fixing electrode in contact with the first base layer at a bottom part of the electrode opening; and a drain electrode below the substrate.

A high frequency RF power transistor includes first and second elongated mesas. In one example, the transistor is part of a millimeter wave MMIC power amplifier. From the top-down perspective, the two mesas are disposed in an off-axis and staggered orientation with respect to one another. A branched gate electrode is formed such that a first branch from a gate signal input location to the first mesa is the same length as a second branch from the input location to the second mesa. Likewise, a branched drain electrode is formed such that a first branch from the first mesa to a drain signal output location is the same length as a second branch from the second mesa to the output location. The off-axis and staggered orientation of the mesas spreads heat generation across the integrated circuit and reduces circuit size in the critical dimension perpendicular to signal flow direction.

A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into both a low voltage transistor structure and a high voltage transistor structure. Within the low voltage transistor structure, a first of two semiconductor material layers may be replaced with a gate stack while the high voltage transistor structure may retain both of two semiconductor material layers. The material stack may also be fabricated into both a transistor structure and a resistor structure. Within the transistor structure, a first of two semiconductor material layers may be replaced with a gate stack while the resistor structure may retain both of two semiconductor material layers.

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

The present disclosure provides a non-planar hole channel transistor and a fabrication method thereof. The non-planar hole channel transistor has a substrate, and a surface of the substrate has a step structure comprising a vertical surface. A non-planar channel layer is epitaxially grown laterally with the vertical surface as a core. A barrier layer is formed on the channel layer, so as to simultaneously form a two-dimensional hole gas and/or a two-dimensional electron gas at an interface between the barrier layer and the channel layer.

A transistor. The transistor includes a top side with V-shaped trenches, wherein inner V-shaped trenches are at least partially conductive, and outer V-shaped trenches are at least partially non-conductive. Methods for producing such a transistor are also described.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.

Semiconductor devices and fabricating methods thereof are provided. The semiconductor device includes vertical transistors each including a semiconductor layer and a gate structure coupled to the semiconductor layer and cup-shaped capacitors coupled with the vertical transistors correspondingly. The semiconductor layer of each vertical transistor includes a vertical portion extending in a vertical direction and a lateral portion extending from a first end of the vertical portion in a lateral direction. The first lateral portions of the semiconductor layers of two adjacent vertical transistors in the lateral direction are connected with each other.

A semiconductor device includes a semiconductor substrate including a semiconductor element, a first surface-side electrode disposed on a first surface of the semiconductor substrate, and a second surface-side electrode disposed on a second surface of the semiconductor substrate. The semiconductor substrate includes a gallium nitride substrate and first column regions and second column regions disposed on a first principal surface of the gallium nitride substrate and alternately arranged along a c-axis direction in the first principal surface. The first column regions are formed of a first nitride semiconductor layer and the second column regions are formed of a second nitride semiconductor layer that is higher in band gap than the first nitride semiconductor layer. The semiconductor element is configured to enable a current to flow between the first surface and the second surface of the semiconductor substrate.