An electrophoresis display with improved micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The height of the partition wall of the micro partition structure is smaller than 25 m.

An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The sum of the data line width and the gate line width is not larger than 10 m. The aperture ratio of the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 80%.

A display panel is provided. The display panel includes a substrate, a gate electrode, an insulating barrier layer, a gate insulating layer, and a silicon-based active layer. The insulating barrier layer is disposed on the gate electrode and the substrate, a band gap width of a material of the insulating barrier layer is greater than a work function of a material of the gate electrode, and the material of the insulating barrier layer includes one or more combinations of diamond, aluminum nitride, boron nitride, silicon oxide, and alumina. The gate insulating layer is disposed on the insulating barrier layer, and a material of the gate insulating layer is silicon nitride. The silicon-based active layer is disposed on the gate insulating layer, and the silicon-based active layer is in contact with the gate insulating layer.

A display apparatus includes an oxide semiconductor pattern disposed on a device substrate and including a channel region disposed between a source region and a drain region, a gate electrode overlapping the channel region of the oxide semiconductor pattern and having a structure in which a first hydrogen barrier layer and a gate conductive layer are stacked, and a gate insulating film disposed between the oxide semiconductor pattern and the gate electrode to expose the source region and the drain region of the oxide semiconductor pattern. The gate electrode exposes a portion of the gate insulating film that is adjacent to the source region and a portion of the gate insulating film that is adjacent to the drain region.

An electrophoresis display with tapered micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The sectional width of the partition wall decreases with a layer number of a polymer stacks forming the partition wall increases.

A display device includes a substrate including a display area and a peripheral area surrounding a portion of the display area, a gate driver disposed in the display area on the substrate, including a driver transistor, and that generates a first gate signal, first pixel members disposed on the gate driver, each including a first pixel transistor, and overlapping the gate driver in a plan view, a connection part disposed in the peripheral area adjacent to the gate driver on the substrate and including a first conductive pattern and a second conductive pattern disposed on the first conductive pattern and connected to the first conductive pattern through a contact hole, a connection line extending from the first conductive pattern and connected to the gate driver, and a gate signal line disposed on the connection line, extending from the second conductive pattern, and connected to each of the first pixel members.

There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.

A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, a third conductive layer over the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer includes a first opening reaching the first conductive layer. The second conductive layer includes a second opening. The first opening and the second opening overlap with each other in a plan view. In the first opening, the first semiconductor layer is in contact with the top surface of the first conductive layer and the side surface of the first insulating layer. In the second opening, the first semiconductor layer is in contact with the side surface of the second conductive layer. The first semiconductor layer includes a region overlapping with the third conductive layer with the second insulating layer therebetween. The side surface of the first insulating layer in the first opening includes a region forming an angle of greater than or equal to 10 and less than 55 with the top surface of the first conductive layer.