H10D86/431

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device that occupies a small area is provided. The semiconductor device includes an oxide semiconductor layer, first to third conductive layers, a first insulating layer, and a second insulating layer. The first conductive layer includes a first metal layer and a first metal oxide layer including the same metal as each other. The first metal layer is electrically connected to the oxide semiconductor layer through the first metal oxide layer. The second conductive layer includes a second metal layer and a second metal oxide layer including the same metal as each other. The second metal layer is electrically connected to the oxide semiconductor layer through the second metal oxide layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The oxide semiconductor layer is in contact with the top surface of the first metal oxide layer, the top surface and a side surface of the second metal oxide layer, and a side surface of the first insulating layer. The second insulating layer is positioned over the oxide semiconductor layer. The third conductive layer is positioned over the second insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer therebetween.

Display device

A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

Performance optimization by sizing gates and source/drain contacts differently for different transistors

A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.