A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the common electrode line. A semiconductor member and a data member are formed on the gate insulating layer. A first passivation layer is formed on the semiconductor member and the data member. A plurality of color filters is formed on the first passivation layer. A conductor layer and a second passivation layer are formed on the plurality of color filters. A first contact hole exposes a common electrode. A second contact hole exposes the drain electrode. The first and second contact holes are formed by a photolithography process. A pixel electrode connected to the drain electrode is formed through the first contact hole. A connecting member connected to the common electrode line and the common electrode is formed through the second contact hole.

The present invention provides a GOA circuit structure for a slim-bezel LCD, including: a latch, a NAND gate, a buffer unit, and a reset unit. An input signal is supplied to the latch and an output signal is supplied from the buffer unit. The buffer unit includes a plurality of TFTs formed of a first metal layer (1), a second metal layer (2), and an active layer (3) arranged between the first metal layer (1) and the second metal layer (2). Each of the TFTs includes a dual-gate arrangement including a bottom gate formed of the first metal layer (1), a source and a drain formed of the second metal layer (2), and a top gate also formed of the second metal layer (2) so that the size of the TFT of the buffer unit can be reduced, the width of buffer unit can be reduced, thereby reducing the width of the GOA circuit and allowing a bezel of the LCD to be slimmer.

A semiconductor device includes a substrate, a first thin film transistor supported on the substrate and having a first active layer that primarily contains a first oxide semiconductor, and second thin film transistor supported on the substrate and having a second active layer that primarily contains a second oxide semiconductor with a higher mobility than the first oxide semiconductor. The first active layer and the second active layer are positioned on the same insulating layer and contact the same insulating layer.

The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer.

A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

A first high voltage semiconductor element, disposed in a substrate, includes first trenches; a first source region and a first drain region; first drift regions having respective ones partially surround the first source region and the first drain region; a first gate insulating layer and a first gate electrode disposed between the first drift regions; and a first high voltage well surrounding the first drift regions. A second high voltage semiconductor element, disposed in the substrate, includes second trenches; a second source region and a second drain region; second drift regions having respective ones partially surround the second source region and the second drain region; a second gate insulating layer and a second gate electrode disposed between the second drift regions; and a second high voltage well surrounding the second drift regions. Depths of the second trenches are disposed to be greater than depths of the first trenches.

An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes a substrate and a thin film transistor layer arranged on the substrate. The thin film transistor layer includes a plurality of thin film transistors. The thin film transistors each include an active layer, a source/drain, a first gate, a second gate, and a first insulating layer. The first gate and the second gate are electrically connected through the through hole. The problems of difficulty in etching and excessively long etching time are avoided while reducing the gate resistance of the thin film transistor.

A display device includes a display panel having a display area and a non-display area, at least one thin-film transistor disposed in the non-display area, at least two or more divided capacitors disposed in the non-display area, and a bridge line for connecting two neighboring divided capacitors with each other among the at least two or more divided capacitors. The non-display area includes a light-blocking film disposed on a substrate and having a stepped first region and a flat second region, and a buffer and gate insulating film disposed on the light-blocking film, and having a bent first region disposed on the stepped first region of the light-blocking layer and a flat second region disposed on the flat second region of the light-blocking layer.

A display device includes: a substrate; a semiconductor layer; a gate electrode overlapping the semiconductor layer; a common voltage line disposed on a same layer as the gate electrode; a common voltage line anti-oxidation layer disposed on the common voltage line; an interlayer insulating layer; source and drain electrodes disposed on the interlayer insulating layer; and a common voltage applying electrode disposed on a same layer as the source electrode and the drain electrode. The common voltage applying electrode is connected to the common voltage line through a first contact hole formed in the interlayer insulating layer, the common voltage line anti-oxidation layer includes an opening overlapping the common voltage line, the interlayer insulating layer is disposed in the opening, a width of the opening is smaller than a width of the common voltage line, and the first contact hole is disposed in the opening in a plan view.

A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 110.sup.19/cm.sup.3 or more by thermal desorption spectroscopy, which is estimated as oxygen molecules. The amount of oxygen molecules released from the fourth insulating film is less than 110.sup.19/cm.sup.3.