GOA CIRCUIT STRUCTURE FOR SLIM-BEZEL LCD

Abstract

The present invention provides a GOA circuit structure for a slim-bezel LCD, including: a latch, a NAND gate, a buffer unit, and a reset unit. An input signal is supplied to the latch and an output signal is supplied from the buffer unit. The buffer unit includes a plurality of TFTs formed of a first metal layer (1), a second metal layer (2), and an active layer (3) arranged between the first metal layer (1) and the second metal layer (2). Each of the TFTs includes a dual-gate arrangement including a bottom gate formed of the first metal layer (1), a source and a drain formed of the second metal layer (2), and a top gate also formed of the second metal layer (2) so that the size of the TFT of the buffer unit can be reduced, the width of buffer unit can be reduced, thereby reducing the width of the GOA circuit and allowing a bezel of the LCD to be slimmer.

Claims

1. A gate-driver-on-array (GOA) circuit structure for a slim-bezel liquid crystal display (LCD), comprising a latch, a NAND gate, a buffer unit, and a reset unit, the latch being electrically connected to the NAND gate and the reset unit, the NAND gate being electrically connected to the latch and the buffer unit, an input signal being supplied to the latch, an output signal being supplied from the buffer unit, wherein the buffer unit comprises a plurality of thin-film transistors (TFTs) formed of a first metal layer, a second metal layer, and an active layer arranged between the first metal layer and the second metal layer, each of the TFTs comprising a dual-gate arrangement, which comprises a bottom gate formed of the first metal layer, a source and a drain formed of the second metal layer, and a top gate also formed of the second metal layer.

2. The GOA circuit structure for a slim-bezel LCD as claimed in claim 1, wherein the source and the drain are respectively located on two sides of the bottom gate and the top gate; the active layer has zones that respectively correspond to the source and the drain of the TFT and are heavily ion doped zones and the active layer has a portion corresponding to a zone between the source and the drain of the TFT and forming a channel zone.

3. The GOA circuit structure for a slim-bezel LCD as claimed in claim 2, wherein the source and the drain of the TFT are each connected by a via to the heavily ion doped zones of the active layer.

4. The GOA circuit structure for a slim-bezel LCD as claimed in claim 3, wherein a bottom gate insulation layer is further arranged between the first metal layer and the active layer and a top gate insulation layer is further arranged between the active layer and the second metal layer; and the vias extend through the top gate insulation layer.

5. The GOA circuit structure for a slim-bezel LCD as claimed in claim 1, wherein the first metal layer is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof.

6. The GOA circuit structure for a slim-bezel LCD as claimed in claim 1, wherein the second metal layer is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof.

7. The GOA circuit structure for a slim-bezel LCD as claimed in claim 1, wherein the active layer is formed of a material of poly-silicon.

8. The GOA circuit structure for a slim-bezel LCD as claimed in claim 4, wherein the bottom gate insulation layer and the top gate insulation layer are formed of a material comprising silicon oxide, silicon nitride, or a combination thereof.

9. A gate-driver-on-array (GOA) circuit structure for a slim-bezel liquid crystal display (LCD), comprising a latch, a NAND gate, a buffer unit, and a reset unit, the latch being electrically connected to the NAND gate and the reset unit, the NAND gate being electrically connected to the latch and the buffer unit, an input signal being supplied to the latch, an output signal being supplied from the buffer unit, wherein the buffer unit comprises a plurality of thin-film transistors (TFTs) formed of a first metal layer, a second metal layer, and an active layer arranged between the first metal layer and the second metal layer, each of the TFTs comprising a dual-gate arrangement, which comprises a bottom gate formed of the first metal layer, a source and a drain formed of the second metal layer, and a top gate also formed of the second metal layer; wherein the first metal layer is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof; wherein the second metal layer is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof; and wherein the active layer is formed of a material of poly-silicon.

10. The GOA circuit structure for a slim-bezel LCD as claimed in claim 9, wherein the source and the drain are respectively located on two sides of the bottom gate and the top gate; the active layer has zones that respectively correspond to the source and the drain of the TFT and are heavily ion doped zones and the active layer has a portion corresponding to a zone between the source and the drain of the TFT and forming a channel zone.

11. The GOA circuit structure for a slim-bezel LCD as claimed in claim 10, wherein the source and the drain of the TFT are each connected by a via to the heavily ion doped zones of the active layer.

12. The GOA circuit structure for a slim-bezel LCD as claimed in claim 11, wherein a bottom gate insulation layer is further arranged between the first metal layer and the active layer and a top gate insulation layer is further arranged between the active layer and the second metal layer; and the vias extend through the top gate insulation layer.

13. The GOA circuit structure for a slim-bezel LCD as claimed in claim 12, wherein the bottom gate insulation layer and the top gate insulation layer are formed of a material comprising silicon oxide, silicon nitride, or a combination thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The technical solution, as well as other beneficial advantages, of the present invention will be apparent from the following detailed description of embodiments of the present invention, with reference to the attached drawing. In the drawing:

[0030] FIG. 1 is a schematic view illustrating the basic operation principle of a GOA (Gate Driver on Array) circuit;

[0031] FIG. 2 is a block diagram showing a basic structure of a GOA circuit with a CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing process;

[0032] FIG. 3 is a top plan view of a buffer unit of a conventional GOA circuit;

[0033] FIG. 4 is a schematic view illustrating a cross-section of FIG. 3 taken along line A-A;

[0034] FIG. 5 is a top plan view showing a GOA circuit structure for a slim-bezel LCD (Liquid Crystal Display) according to the present invention; and

[0035] FIG. 6 is a schematic view illustrating a cross-section of FIG. 5 taken along line B-B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] To further expound the technical solution adopted in the present invention and the advantages thereof, a detailed description is given to a preferred embodiment of the present invention and the attached drawings.

[0037] The present invention provides a GOA (Gate Driver on Array) circuit structure for a slim-bezel LCD (Liquid Crystal Display). Referring to FIGS. 2, 5, and 6, the GOA circuit structure of the present invention comprises: a latch, a NAND gate, a buffer unit, and a reset unit. The latch is electrically connected to the NAND gate and the reset unit. The NAND gate is electrically connected to the latch and the buffer unit. An input signal and a first clock signal are supplied to the latch and a second clock signal is fed to the NAND gate. An output signal is supplied from the buffer unit.

[0038] The buffer unit comprises a plurality of TFTs (Thin-Film Transistors) that is made up of a first metal layer 1, a second metal layer 2, and an active layer 3 arranged between the first metal layer 1 and the second metal layer 2. Each of the TFTs comprises a dual-gate arrangement that comprises a bottom gate formed of the first metal layer 1, a source and a drain formed of the second metal layer 2, and a top gate also formed of the second metal layer 2.

[0039] Specifically, the source and the drain are respectively located on two sides of the bottom gate and the top gate. The active layer 3 has zones that respectively correspond to the source and the drain of the TFT and are heavily ion doped zones 31. The active layer 3 has a portion corresponding to a zone between the source and the drain of the TFT and forming a channel zone 32.

[0040] Further arranged between the first metal layer 1 and the active layer 3 is bottom gate insulation layer 5 and further arranged between the active layer 3 and the second metal layer 2 is a top gate insulation layer 6. The source and the drain of the TFT are respectively connected by vias 61 that extend through the top gate insulation layer 6 to the heavily ion doped zones 31 of the active layer 3.

[0041] The first metal layer 1 is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof.

[0042] The second metal layer 2 is formed of a material comprising one of molybdenum, titanium, aluminum, copper, and nickel or a stacked combination of multiple ones thereof.

[0043] The active layer 3 is formed of a material of poly-silicon.

[0044] The bottom gate insulation layer 5 and the top gate insulation layer 6 are each formed of a material of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0045] In the above-described buffer unit, the TFT comprises a bottom gate that is formed of the first metal layer 1 and located under the channel zone 32 of the active layer 3 and a top gate that is formed of the second metal layer 2 and located above the channel 32 of the active layer 3, the channel zone 32 of the active layer 3 having a large thickness and thus reduced resistance, so that the driving capability of the TFT of the buffer unit is significantly increased, whereby under the condition of identical driving capability, the size of the TFT of the buffer unit can be reduced and thus, the width of the buffer unit can be reduced and the width of the GOA circuit can be reduced to make it possible for a bezel of an LCD to be made even slimmer. For example, under the condition of identical driving capability, the buffer unit of a conventional GOA circuit has a width of around 300 m, while the buffer unit of the GOA circuit structure of the present invention has a width that is reduced to around 150 m so that compared to the prior art, the GOA circuit structure of the present invention allows the width of the GOA circuit and the width of the bezel of the LCD to be reduced by around 150 m.

[0046] In summary, the present invention provides a GOA circuit structure for a slim-bezel LCD, which comprises a buffer unit having therein a TFT that comprises a bottom gate formed of a first metal layer and located under a channel zone of an active layer and a top gate formed of a second metal layer and located above the channel zone of the active layer and the channel zone of the active layer has a large thickness and thus reduced resistance so as to significantly increase the driving capability of the TFT of the buffer unit. Under the condition of identical driving capability, the size of the TFT of the buffer unit can be reduced thereby reducing the width of the buffer unit, and reducing the with of the GOA circuit, and allowing a bezel of the LCD to be made slimmer.

[0047] Based on the description given above, those having ordinary skills of the art may easily contemplate various changes and modifications of the technical solution and technical ideas of the present invention and all these changes and modifications are considered within the protection scope of right for the present invention.